tag: transmission electron microscopy

Buried Si/SiGe Interfaces Investigated Using Soft X-Ray Reflectometry and STEM-EDX
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Interface sharpness in stacked thin film structures: a comparison of soft X-ray reflectometry and transmission electron microscopy" was published by researchers at Physikalisch-Technische Bundesanstalt (PTB), imec, and Thermo Fisher Scientific Inc. The paper states: "A key element of semiconductor fabrication is the precise deposition of thin films. Among other... » read more

Front-end patterning and epitaxy approach on Si photonics 220nm SOI substrates
By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Lateral Tunnel Epitaxy of GaAs in Lithographically Defined Cavities on 220 nm Silicon-on-Insulator" was published by researchers at Cardiff University and University of Southampton. Abstract "Current heterogeneous Si photonics usually bond III–V wafers/dies on a silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by di... » read more

Integration Of Layered Semimetals With Conventional CMOS Platform
By Technical Paper Link - 27 Sep, 2023 - Comments: 0

A technical paper titled “Layered semimetal electrodes for future heterogeneous electronics” was published by researchers at IIT Madras and Indian Institute of Science Education and Research. Abstract: "Integration of the emerging layered materials with the existing CMOS platform is a promising solution to enhance the performance and functionalities of the future CMOS based integrated cir... » read more

Investigating The Ru/Ta Bilayer As An Alternative EUV Absorber To Mitigate Mask 3D Effects
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “Ru/Ta bilayer approach to EUV mask absorbers: Experimental patterning and simulated imaging perspective” was published by researchers at KU Leuven and imec. Abstract: "The optical properties and geometry of EUV mask absorbers play an essential role in determining the imaging performance of a mask in EUV lithography. Imaging metrics, including Normalized Imag... » read more

Design of Selective Deposition Processes For Nanoscale Electronic Devices
By Technical Paper Link - 27 Jun, 2023 - Comments: 0

A technical paper titled “Quantified Uniformity and Selectivity of TiO2 Films in 45-nm Half Pitch Patterns Using Area-Selective Deposition Supercycles” was published by researchers at IMEC, North Carolina State University, and KU Leuven. Abstract: "Area-selective deposition (ASD) shows great promise for sub-10 nm manufacturing in nanoelectronics, but significant challenges remain in scali... » read more

New Imaging Tech Finds Buried Defects
By Shinsuke Mizuno - 23 May, 2019 - Comments: 0

By Shinsuke Mizuno and Vadim Kuchik Defects and contamination on the wafer can slow process development times and limit performance and yield. As chips get more complex, more defects can become buried within the increasing number of layers in the design. Finding and analyzing these buried defects is a major challenge for the industry, especially during the early learning cycles of new manufa... » read more

FinFET Metrology Challenges Grow
By Mark LaPedus - 17 May, 2018 - Comments: 1

Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward... » read more

Waiting For Next-Gen Metrology
By Mark LaPedus - 21 May, 2015 - Comments: 0

Chipmakers continue to march down the various process nodes, but the industry will require new breakthroughs to extend IC scaling at 10nm and beyond. In fact, the industry will require innovations in at least two main areas—patterning and the [getkc id="36" comment="Interconnect"]. There are other areas of concern, but one technology is quickly rising near the top of the list—metrology.... » read more

Searching For 3D Metrology
By Mark LaPedus - 19 Mar, 2015 - Comments: 3

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

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