Curvilinear Design Benefits For Wafers


Throughout this blog series the focus has been on curvilinear photomasks – the benefits, enablers, and challenges. It leads to the obvious question that Aki Fujimura, CEO of D2S, put to the panel of luminaries. If leading-edge mask shops are ready for curvilinear shapes on mask enabled by curvilinear ILT, multi-beam mask writers and the mask design chain, can we have curvilinear target shapes... » read more

Gearing Up For High-NA EUV


The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task. ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems... » read more

What’s Next For Transistors And Chiplets


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Week In Review: Manufacturing, Test


Chipmakers TSMC posted its results for the quarter and confirmed its long-awaited plans to build a fab in Japan. It’s not a leading-edge fab, but rather a plant for 28nm/22nm processes. “The company confirmed plans to build a new fab in Japan for 22nm + 28nm,” said Aaron Rakers, an analyst at Wells Fargo, in a research note. “An average 22/28nm fab costs ~$4-5B range per 45k wspm. Fab ... » read more

Week In Review: Manufacturing, Test


Government policy Hoping to resolve the ongoing worldwide chip shortage situation, the U.S. Department of Commerce late last month launched a “request for information (RFI)” initiative, which involved sending questionnaires to various semiconductor companies. The U.S. government is asking all parts of the supply chain – producers, consumers, and intermediaries – to voluntarily share in... » read more

Week In Review: Design, Low Power


Arteris IP plans to become a public company. It filed a registration statement with the SEC for an IPO, and intends to list on Nasdaq. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP provides network-on-chip interconnect IP, cache coherent interconnects, and packages to speed functional safety certification alongside IP d... » read more

Week In Review: Manufacturing, Test


Markets Worldwide semiconductor industry revenue is expected to grow 17.3% in 2021, compared with 10.8% in 2020, according to a new IDC report. Segment breakdown is as follows: [table id=5 /] “Semiconductor wafer prices increased in 1H21 and IDC expects increases to continue for the rest of 2021 due to material costs and opportunity cost in mature process technologies. Overall, IDC pre... » read more

Week In Review: Design, Low Power


MoSys, a provider of SRAM solutions and networking accelerators, and Peraso Technologies, a provider of 5G mmWave devices, are merging. Stockholders of Peraso are expected to hold a 61% equity interest in the combined company, with the remaining 39% equity interest to be retained by the stockholders of MoSys. Peraso CEO Ronald Glibbery said, "By joining with MoSys, we believe we can deliver a b... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Arm announced a new software architecture, two reference hardware implementations, and its role leading a new industry group that will work on open-source software for automotive use. The Scalable Open Architecture for Embedded Edge (SOAFEE) is based on Arm’s Project Cassini and SystemReady, aims to help the automotive industry move to software-defined systems by tackling the comp... » read more

System-In-Package Thrives In The Shadows


IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

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