Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V


A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

Chip Industry’s Technical Paper Roundup: Jan. 31


New technical papers added to Semiconductor Engineering’s library. [table id=77 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting l... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs


A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models


A technical paper titled "Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation" was published by researchers at MIT (CSAIL), Argonne National Lab, and TU Munich. The paper was a Best Paper Finalist and a Best Student Paper winner at SuperComputing 2022. Find the technical paper here. Published November 2022. The work "demonstrates how Enzyme opti... » read more

Week 21 – Visiting Detroit


Who would have thought I’d end up sitting outside in the sunshine in downtown Detroit writing the first draft for my next blog. I’m here with a few of my Mentor colleagues to attend SAE Convergence and to have a discussion with GM about a possible DAC keynote. Stay tuned (and keep your fingers crossed) — I hope to tell you more about that at a later time. SAE Convergence is a two-day conf... » read more

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