tag: University of Bologna

A Hierarchical Instruction Cache Tailored To Ultra-Low-Power Tightly-Coupled Processor Clusters
By Technical Paper Link - 15 Sep, 2023 - Comments: 0

A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves Technologies. Abstract: "High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) ha... » read more

Week In Review: Design, Low Power
By Susan Rambo - 14 Jul, 2023 - Comments: 0

DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing. Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler EDA and IP remain strong, approaching $4 billion in Q1, according to ... » read more

Chip Industry’s Technical Paper Roundup: June 20
By Liz Allan - 20 Jun, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=112 /] » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Chip Industry’s Technical Paper Roundup: Apr. 18
By Linda Christensen - 18 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=93 /]   If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involv... » read more

Scalable, Shared-L1-Memory Manycore RISC-V System
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory" was published by researchers at ETH Zurich and University of Bologna. Abstract: "Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly... » read more

Chip Industry’s Technical Paper Roundup: Apr. 10
By Linda Christensen - 10 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=92 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14
By Linda Christensen - 14 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Hardware Virtualization Support in the RISC-V CVA6 Core
By Technical Paper Link - 08 Mar, 2023 - Comments: 0

A new technical paper titled "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration" was published (preprint) by researchers at Universidade do Minho, University of Bologna, and ETH Zurich. Abstract "Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream comp... » read more

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