tag: University of Bologna

RISC-V Pushes Into The Mainstream
By Marie C. Baca and Ed Sperling - 21 Dec, 2022 - Comments: 1

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications. These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set ar... » read more

Chip Industry’s Technical Paper Roundup: Dec. 20
By Linda Christensen - 20 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=71 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us po... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

Chip Industry’s Technical Paper Roundup: Dec. 5
By Linda Christensen - 05 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=67 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for u... » read more

An Arrangement of Chiplets That Outperforms A Grid Arrangement (ETH Zurich / U. of Bologna)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A research paper titled "HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement" was published by researchers at ETH Zurich and University of Bologna. Abstract: "2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects ... » read more

Technical Paper Round-up: August 8
By Linda Christensen - 08 Aug, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=44 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores
By Technical Paper Link - 03 Aug, 2022 - Comments: 0

This new technical paper titled "RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs" was published by researchers at University of Bologna and ETH Zurich. According to their abstract: "One of the key stumbling stones is the need for parallel floating-point operations, which are considered unaffordable on sub-100 mW extre... » read more

Technical Paper Round-up: July 11
By Linda Christensen - 11 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=38 /]   Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

ISA Extension For Low-Precision NN Training On RISC-V Cores
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores" from researchers at IIS, ETH Zurich; DEI, University of Bologna; and Axelera AI. Abstract "Low-precision formats have recently driven major breakthroughs in neural network (NN) training and inference by reducing the memory footprint of the N... » read more

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