Chip Industry’s Technical Paper Roundup: June 20

Chiplet-based AI accelerator; MOSFET for neuromorphic computing; RISC-V platform for domain-specific accelerators; colloidal quantum dots; tools for HPC systems; DRAM subarrays and rowhammer; architecture for quantum RAM; eliminating the von-Neumann bottleneck; object detection CNN; the CuQuantum framework.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning Auburn University
Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing Indian Institute of Technology (IIT) Bombay
Systems Architecture for Quantum Random Access Memory Yale University, AWS Center for Quantum Computing, and California Institute of Technology
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In ETH Zurich and University of Bologna
Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study Barcelona Supercomputing Center and FORTH
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands Seoul National University and University of Illinois at Urbana-Champaign
Non-volatile heterogeneous III-V/Si photonics via optical charge-trap memory Hewlett Packard Enterprise
TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers ETH Zurich
Enabling metallic behaviour in two-dimensional superlattice of semiconductor colloidal quantum dots RIKEN, Tokyo Institute of Technology, University of Tokyo, and Tokyo University of Agriculture and Technology

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