Chip Industry’s Technical Paper Roundup: October 9


New technical papers added to Semiconductor Engineering’s library this week. [table id=153 /] More Reading Technical Paper Library home » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs


A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Novel NVM Devices and Applications (UC Berkeley)


A dissertation titled “Novel Non-Volatile Memory Devices and Applications” was submitted by a researcher at University of California Berkeley. Abstract Excerpt "This dissertation focuses on novel non-volatile memory devices and their applications. First, logic MEM switches are demonstrated to be operable as NV memory devices using controlled welding and unwelding of the contacting electro... » read more

Chip Industry’s Technical Paper Roundup: October 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs


A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich. Abstract: "Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the co... » read more

Chip Industry Technical Paper Roundup: August 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

A Performance-Aware Framework For Co-Optimizing Floorplan And Performance Of Chiplet-Based Architecture


A technical paper titled “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration” was published by researchers at Chinese University of Hong Kong and University of California Berkeley. Abstract: "A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs),... » read more

Week In Review: Auto, Security, Pervasive Computing


The Biden-Harris Administration announced the U.S. Cyber Trust Mark, a cybersecurity certification and labeling program to help consumers choose smart devices less vulnerable to cyberattacks. The Federal Communications Commission (FCC) is applying to register the Cyber Trust Mark with the U.S. Patent and Trademark Office and it would appear on qualifying smart products, including refrigerators,... » read more

Chip Industry’s Technical Paper Roundup: July 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=114 /] (more…) » read more

Demonstrating The Utility Of Quantum Computing In A Pre-Fault-Tolerant Era


A technical paper titled “Evidence for the utility of quantum computing before fault tolerance” was published by researchers at IBM Quantum, University of California Berkeley, RIKEN, and Lawrence Berkeley National Laboratory. Abstract: "Quantum computing promises to offer substantial speed-ups over its classical counterpart for certain problems. However, the greatest impediment to realizi... » read more

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