tag: verification

The True Cost Of Software Changes
By Brian Bailey - 22 Jun, 2023 - Comments: 2

Safety and security are considered to be important in a growing number of markets and applications. Guidelines are put in place for the processes used to develop either the hardware or the software, but what they seem to ignore is that neither exists in a vacuum. They form a system when put together. Back when I was developing tools for hardware-software co-verification, there were fairly co... » read more

Overcoming Regression Debug Challenges With Machine Learning
By Robert Ruiz - 22 Jun, 2023 - Comments: 0

Development of a modern semiconductor requires running many electronic design automation (EDA) tools many times over the course of the project. Every stage, from architectural exploration and design to final implementation and manufacturing preparation, has multiple methodology loops that must be repeated again and again. Even in such a complex development flow, functional simulation stands ... » read more

Shift Left With Calibre To Optimize IC Design Flow Productivity, Design Quality, And Time To Market
By Siemens EDA - 21 Jun, 2023 - Comments: 0

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full sign-off verification. However, waiting until sign-off verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware... » read more

Issues and Opportunities in Using LLMs for Hardware Design
By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A technical paper titled "Chip-Chat: Challenges and Opportunities in Conversational Hardware Design" was published by researchers at NYU and University of New South Wales. Abstract "Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before syn... » read more

Welcome To EDA 4.0 And The AI-Driven Revolution
By Dan Yu - 01 Jun, 2023 - Comments: 1

By Dan Yu, Harry Foster, and Tom Fitzpatrick Welcome to the era of EDA 4.0, where we are witnessing a revolutionary transformation in electronic design automation driven by the power of artificial intelligence. The history of EDA can be delineated into distinct periods marked by significant technological advancements that have propelled faster design iterations, improved productivity, and fu... » read more

A Formal-Based Approach For Efficient RISC-V Processor Verification
By Codasip - 24 May, 2023 - Comments: 0

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new fu... » read more

ML Automotive Chip Design Takes Off
By Ann Mutschler - 04 May, 2023 - Comments: 0

Machine learning is increasingly being deployed across a wide swath of chips and electronics in automobiles, both for improving reliability of standard parts and for the creation of extremely complex AI chips used in increasingly autonomous applications. On the design side, the majority of EDA tools today rely on reinforcement learning, a machine learning subset of AI that teaches a machine ... » read more

Accelerating Coverage Closure With AI-Based Verification Space Optimization
By Synopsys - 03 May, 2023 - Comments: 0

Coverage is at the heart of all modern semiconductor verification. There is no maxim more fundamental to this process than “if you haven’t exercised it, you haven’t verified it.” Although covering a particular aspect of a chip design does not guarantee that all bugs are found — bug effect propagation and checker quality are also key factors — it is certainly true that bugs cannot po... » read more

Can AI Write RTL?
By Brian Bailey - 01 May, 2023 - Comments: 1

Just a few months ago, generative AI was just a promise about what would be possible in the future. Today, nearly everyone with an ounce of curiosity has tried ChatGPT. Most people appear to be somewhat impressed with what it can do, but at the same time see the limitations that it has. As Dean Drako, founder of several companies, told me: "Recently, I needed to write a patent. I described t... » read more

RISC-V Driving New Verification Concepts
By Brian Bailey - 12 Apr, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

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