tag: verification

Can AI Write RTL?
By Brian Bailey - 01 May, 2023 - Comments: 1

Just a few months ago, generative AI was just a promise about what would be possible in the future. Today, nearly everyone with an ounce of curiosity has tried ChatGPT. Most people appear to be somewhat impressed with what it can do, but at the same time see the limitations that it has. As Dean Drako, founder of several companies, told me: "Recently, I needed to write a patent. I described t... » read more

RISC-V Driving New Verification Concepts
By Brian Bailey - 12 Apr, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

What’s Required To Secure Chips
By Ed Sperling - 06 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

Do Necessary Tools Exist For RISC-V Verification?
By Brian Bailey - 30 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner... » read more

AI Becoming More Prominent In Chip Design
By Ed Sperling - 27 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about the role of AI in managing data and improving designs, and its growing role in pathfinding and preventing silent data corruption, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta... » read more

RISC-V Disrupting EDA
By Brian Bailey - 23 Mar, 2023 - Comments: 3

The electronic design automation (EDA) industry started in the 1980s and primarily was driven by the test and PCB industries. The test industry was focused on simulation so that test vector sets could be developed and optimized. The PCB industry needed help managing complexity as system sizes grew. That complexity soon was eclipsed by IC complexity and the costs associated with making a mist... » read more

How AI Drives Faster Verification Coverage And Debug For First-Time-Right Silicon
By Taruna Reddy - 23 Mar, 2023 - Comments: 0

By Taruna Reddy and Robert Ruiz These days, the question is less about what AI can do and more about what it can’t do. From talk-of-the-town chatbots like ChatGPT to self-driving cars, AI is becoming pervasive in our everyday lives. Even industries where it was perhaps an unlikely fit, like chip design, are benefiting from greater intelligence. What if one of the most laborious, time-co... » read more

System-on-Chip Design In The Cloud: One Size Does Not Fit All
By Nebabie Kebebew - 23 Mar, 2023 - Comments: 0

At an increasing pace, companies in the semiconductor ecosystem have started seriously considering the cloud for computing and storage. Some have migrated, and others are evaluating the cloud technology choices and are sizing the business impact and benefits to make the leap. Through key adoption reports, the cloud environment is proving to be beneficial for System-on-Chip (SoC) designers by pr... » read more

What Makes RISC-V Verification Unique?
By Brian Bailey - 09 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner... » read more

Agile HW Design: Fully Automatic Equivalence Checking Workflow
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "An Equivalence Checking Framework for Agile Hardware Design" was published by researchers at Portland State University and Intel. Abstract "Agile hardware design enables designers to produce new design iterations efficiently. Equivalence checking is critical in ensuring that a new design iteration conforms to its specification. In this paper, we introduce an eq... » read more

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