tag: verification

EDA, IP Fundamentals Shift As Market Soars
By Ed Sperling - 10 Jul, 2023 - Comments: 0

EDA tools and IP continued their double-digit growth trajectory this year, despite a downturn in consumer electronics and a continued shortage of key components that took a large bite out of the semiconductor market as a whole. A just-released report from the ESD Alliance showed a 12% increase in revenue for Q1, increasing to $3.95 billion compared with $3.53 billion in the same period in 20... » read more

How To Use S-Parameters For Power Module Verification
By Wilfried Wessel - 06 Jul, 2023 - Comments: 0

By Wilfried Wessel (Siemens EDA), Simon Liebetegger (University of Applied Sciences Darmstadt), and Florian Bauer (Siemens EDA) Power modules are high-power switching circuits that convert DC- in AC-currents in electric vehicles, renewable energy, and many more applications. New materials [14] and device technologies [14], such as wide bandgap semiconductors, including silicon carbide (SiC) ... » read more

Challenges Grow For Data Management And Sharing In EDA
By Ed Sperling - 29 Jun, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about more openness in EDA data, how increased complexity is affecting time to working silicon, and the impact of geopolitics, with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business U... » read more

Self-Driving Cars: Formalization and Verification Of The Responsibility-Sensitive Safety (RSS) Model
By Technical Paper Link - 28 Jun, 2023 - Comments: 0

A technical paper titled “Slow Down, Move Over: A Case Study in Formal Verification, Refinement, and Testing of the Responsibility-Sensitive Safety Model for Self-Driving Cars” was published by researchers at Carnegie Mellon University. Abstract: "Technology advances give us the hope of driving without human error, reducing vehicle emissions and simplifying an everyday task with the futur... » read more

Verification And Test Of Safety And Security
By Brian Bailey - 22 Jun, 2023 - Comments: 0

Functional verification can cost as much as design, but new capabilities are piling onto an already stressed verification methodology, leaving solutions fragmented and incomplete. In a perfect world, a semiconductor device would be verified to operate according to its complete specification, and continue to operate correctly over the course of its useful life. The reality, however, is this i... » read more

The True Cost Of Software Changes
By Brian Bailey - 22 Jun, 2023 - Comments: 2

Safety and security are considered to be important in a growing number of markets and applications. Guidelines are put in place for the processes used to develop either the hardware or the software, but what they seem to ignore is that neither exists in a vacuum. They form a system when put together. Back when I was developing tools for hardware-software co-verification, there were fairly co... » read more

Overcoming Regression Debug Challenges With Machine Learning
By Robert Ruiz - 22 Jun, 2023 - Comments: 0

Development of a modern semiconductor requires running many electronic design automation (EDA) tools many times over the course of the project. Every stage, from architectural exploration and design to final implementation and manufacturing preparation, has multiple methodology loops that must be repeated again and again. Even in such a complex development flow, functional simulation stands ... » read more

Shift Left With Calibre To Optimize IC Design Flow Productivity, Design Quality, And Time To Market
By Siemens EDA - 21 Jun, 2023 - Comments: 0

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full sign-off verification. However, waiting until sign-off verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware... » read more

Issues and Opportunities in Using LLMs for Hardware Design
By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A technical paper titled "Chip-Chat: Challenges and Opportunities in Conversational Hardware Design" was published by researchers at NYU and University of New South Wales. Abstract "Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before syn... » read more

Welcome To EDA 4.0 And The AI-Driven Revolution
By Dan Yu - 01 Jun, 2023 - Comments: 1

By Dan Yu, Harry Foster, and Tom Fitzpatrick Welcome to the era of EDA 4.0, where we are witnessing a revolutionary transformation in electronic design automation driven by the power of artificial intelligence. The history of EDA can be delineated into distinct periods marked by significant technological advancements that have propelled faster design iterations, improved productivity, and fu... » read more

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