tag: verification

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

A Guide To SDC-Based Timing Intent Verification With Questa One
By Siemens EDA - 16 Jun, 2025 - Comments: 0

As semiconductor designs continue to grow in complexity and timing margins become increasingly constrained, achieving predictable timing closure has evolved from a best practice into a critical requirement for first-pass silicon success. At the heart of this process lies the timing constraint file, i.e., the SDC (Synopsys Design Constraints), which defines the intended timing behavior of the de... » read more

Smarter, Faster, Leaner: Rethinking Verification For The Modern Era
By Harry Foster - 12 Jun, 2025 - Comments: 0

Verification isn’t just another step in the semiconductor design process—it’s increasingly the step that defines whether teams hit their schedules or miss the mark. With skyrocketing design complexity, accelerated development timelines, and persistent engineering shortages, the industry is feeling the pressure. Traditional methods aren’t keeping pace. At Siemens, we’ve been rethink... » read more

Verification Software And Methodology Insights
By Robbie O'Sullivan - 12 Jun, 2025 - Comments: 0

Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025. Among the many engaging sessions, the Verification Software track highlighted how leading companies are advancing verification methodologies to meet the demands of increasingly complex designs. The track featured seven presentations from industry leaders, each offering a unique perspective on how SVG’s verif... » read more

Agentic AI In Chip Design
By Ann Mutschler - 11 Jun, 2025 - Comments: 1

Large language models (LLMs) like ChatGPT are just the starting point for generating content with AI. The next phase will be about harnessing LLMs with agents, providing automated feedback and improvements in performance and accuracy. Mehir Arora, backend engineer at ChipAgents, talks about the impact this can have on EDA and chip design, allowing smaller teams to compete with larger teams, and... » read more

Closing The RISC-V Verification Disconnect
By Larry Lapides - 29 May, 2025 - Comments: 0

With the explosive adoption of RISC-V processors, processor verification has become a hot topic. This is due both to the criticality of the processor IP in the SoC and to the fact that many experienced SoC verification engineers are doing their first processor verification project. While there are similarities between SoC verification and processor verification, there are also significant diffe... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Intent Meets Implementation
By Siemens EDA - 15 May, 2025 - Comments: 0

Power efficiency has become a must-have in today’s ASIC and SoC designs. It’s no longer just about squeezing out more performance. It’s about doing so without draining the battery, wasting energy or overheating the system. Whether the chip is headed for a smartphone, a server rack in an AI datacenter or the control system of an autonomous vehicle, managing power wisely is as critical as m... » read more

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle
By Chandu Challapalli - 15 May, 2025 - Comments: 0

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

Extra Safety Measures Needed For Aerospace ICs
By Liz Allan - 01 May, 2025 - Comments: 0

Aerospace safety requirements and standards vary depending on whether a spacecraft is manned or unmanned, and how crucial the mission is. The defense contractors designing these spacecraft take various approaches to functional safety based on how critical a component is for the mission to succeed. While losing a few images during an Earth-bound observation may not matter, losing a satellite ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy