tag: verification

Tackling Safety And Security
By Brian Bailey - 10 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Open Source Processors: Fact Or Fiction?
By Brian Bailey - 27 Jun, 2019 - Comments: 3

Open source processors are rapidly gaining mindshare, fueled in part by early successes of RISC-V, but that interest frequently is accompanied by misinformation based on wishful thinking and a lack of understanding about what exactly open source entails. Nearly every recent conference has some mention of RISC-V in particular, and open source processors in general, whether that includes keyno... » read more

Verification In The Cloud
By Ed Sperling - 27 Jun, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks with Semiconductor Engineering about what’s changed for EDA in the cloud, why it has taken so long, and what new benefits the cloud will offer. Rules have changed at foundries, and the customer base for designs is evolving. » read more

Who’s Responsible For Security Breaches?
By Brian Bailey - 24 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Unveil The Mystery Of Code Coverage In Low-Power Designs: Achieving Power Aware Verification
By Mentor, a Siemens Business - 12 Jun, 2019 - Comments: 0

This paper discusses challenges in code coverage of low-power designs and approaches to overcome those challenges. Also explained is how total coverage results can be visualized in order to achieve verification closure in significantly less time. To read more, click here. » read more

From Constraints To Tape-Out: Towards A Continuous AMS Design Flow
By Fraunhofer IIS/EAS - 12 Jun, 2019 - Comments: 0

The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

Disregard Safety And Security At Your Own Peril
By Brian Bailey - 10 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Artificial Intelligence: Let Us Get The Math Right First!
By Ravindra Aneja - 06 Jun, 2019 - Comments: 0

Artificial intelligence is a hot topic these days and therefore doesn’t require a repeat of the current and future potential uses for AI. For most people, it means technology advancements on the software side. But if you ask people who are very close to this technology domain, building your own optimized hardware chips is where a significant part of the competitive edge lies. A few days ba... » read more

DAC 2019: Day 1
By Brian Bailey - 04 Jun, 2019 - Comments: 2

The last time that DAC was in Las Vegas was 2001. Much has changed since then. The first day kicked off with the usual ceremonies and then two short keynotes. A change from previous years is that keynotes are now on the show floor. This is presumably to ensure that once the keynotes are over, everyone sees the vendor booths. During the commencement session, it was also announced that all cof... » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

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