tag: verification

AI, Rising Chip Complexity Complicate Prototyping
By Karen Heyman - 24 Aug, 2023 - Comments: 0

Prototyping, an essential technology for designing complex chips in tight market windows, is becoming significantly more challenging for the growing number of designs that include AI/ML. Prototyping remains one of the foundational pillars of the whole shift left movement, allowing software to be developed and tested before actual silicon is available. That, in turn, enables multiple teams t... » read more

The Four Foundational Pillars Of Calibre Shift Left Solutions For IC Design And Implementation Flows
By Siemens EDA - 23 Aug, 2023 - Comments: 0

As the semiconductor industry approaches a new era of digital transformation, design companies everywhere are turning to shift left strategies to address challenges that reduce design cycles while maximizing productivity, optimizing resource efficiency, ensuring design quality, and accelerating time to market. To overcome these challenges in IC design, Calibre shift left technologies include to... » read more

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

New Technology Accelerates Multi-Die System Simulation
By Taruna Reddy - 27 Jul, 2023 - Comments: 0

AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

Using AI To Close Coverage Gaps
By Ed Sperling - 26 Jul, 2023 - Comments: 0

Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

Ditch The Glitch
By Ramsay Allen - 11 Jul, 2023 - Comments: 0

To support the ever-growing performance demands of cutting-edge applications like automotive and hyperscaler, SoC complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To keep up with these demands, design-for-test (DFT) logic must also evolve to ensure greater levels of test robustness and silicon health. The “Shift left” concept which... » read more

EDA, IP Fundamentals Shift As Market Soars
By Ed Sperling - 10 Jul, 2023 - Comments: 0

EDA tools and IP continued their double-digit growth trajectory this year, despite a downturn in consumer electronics and a continued shortage of key components that took a large bite out of the semiconductor market as a whole. A just-released report from the ESD Alliance showed a 12% increase in revenue for Q1, increasing to $3.95 billion compared with $3.53 billion in the same period in 20... » read more

How To Use S-Parameters For Power Module Verification
By Wilfried Wessel - 06 Jul, 2023 - Comments: 0

By Wilfried Wessel (Siemens EDA), Simon Liebetegger (University of Applied Sciences Darmstadt), and Florian Bauer (Siemens EDA) Power modules are high-power switching circuits that convert DC- in AC-currents in electric vehicles, renewable energy, and many more applications. New materials [14] and device technologies [14], such as wide bandgap semiconductors, including silicon carbide (SiC) ... » read more

Challenges Grow For Data Management And Sharing In EDA
By Ed Sperling - 29 Jun, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about more openness in EDA data, how increased complexity is affecting time to working silicon, and the impact of geopolitics, with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business U... » read more

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