tag: verification

From Discovery To High-Speed Delivery: A Unified Verification Approach For UCIe 3.0 Features And Manageability
By Ujjwal Negi - 11 Sep, 2025 - Comments: 0

By Ujjwal Negi and Prashant Dixit The Universal Chiplet Interconnect Express (UCIe) standard is redefining multi-die integration, enabling high-performance, scalable connections between heterogeneous chiplets. UCIe 2.0 introduced a dedicated manageability layer — a control plane for configuring, monitoring, and coordinating chiplet management elements independently from mainband and sideba... » read more

The Demise Of Static Timing Verification?
By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

Verifying The Evolving UCIe Landscape
By Siemens EDA - 10 Sep, 2025 - Comments: 0

This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One Avery VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table setup for both direct an... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 28 Aug, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

How To Transform Verification Time-To-Results
By Priyank Jain - 28 Aug, 2025 - Comments: 0

The clock is ticking. Your team has just completed another full-chip DRC run on a complex 5nm SoC, and the results are overwhelming: millions of violations across hundreds of blocks. With tape-out deadlines approaching, you need to quickly identify which issues are critical, which are systematic and which blocks require immediate attention. Every day spent in DRC debug is a day delayed to marke... » read more

Verification Fails To Keep Up
By Brian Bailey - 28 Aug, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

6G System Design: Realistic Modeling, Simulation and Verification of Next Generation Wireless Systems
By Keysight - 27 Aug, 2025 - Comments: 0

As 6G envisions the convergence of ultra-fast communications, integrated sensing, and native AI capabilities across diverse environments — including terrestrial, aerial, and satellite domains — SystemVue emerges as a high-fidelity RF digital twin environment. It bridges the gap between the initial design and development and physical-layer hardware by accurately modeling RF impairments, phas... » read more

Multi-Modal AI In EDA Development Flows
By Brian Bailey - 31 Jul, 2025 - Comments: 0

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

Questa One Avery VIP: Accelerated Confidence In Complex Protocol Verification
By Siemens EDA - 21 Jul, 2025 - Comments: 0

In today’s rapidly advancing digital landscape, the role of functional verification has never been more critical. As systems become increasingly complex, ensuring their reliability and performance poses significant challenges for both design and verification engineers. The stakes are high; verification failures can lead to costly recalls, safety risks, and damage to brand reputation. The late... » read more

RTL Signoff vs. Functional Signoff: What’s The Difference?
By Bradley Geden - 17 Jul, 2025 - Comments: 1

By Bradley Geden and Manoz Palaparthi In semiconductor design, “signoff” is often treated as a single milestone. In practice, however, it encompasses distinct verification phases with unique objectives. Functional signoff and RTL signoff represent two such phases. Both are essential, and each one is focused on different facets of correctness. While functional signoff verifies whether ... » read more

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