tag: verification

Enhancing PCIe 6.0 Performance: Flit Sequence Numbers And Selective NAK Explained
By Felipe Gonçalves - 30 Oct, 2025 - Comments: 0

The Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction layer packet (TLP) sequence numbering, along with its associated acknowledgment and replay protocols. What is a Flit Sequence Number? Historically, each TLP carried an explicit sequence number, which, while con... » read more

Advances In Formal Verification Technology
By Brian Bailey - 30 Oct, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Raising The Bar In Mission-Critical Verification
By Siemens EDA - 09 Oct, 2025 - Comments: 0

The 2024 Siemens EDA and Wilson Research Group Functional Verification Study provides an in-depth analysis of current trends in FPGA design and verification, with a particular focus on the aerospace and defense (A&D) sector. The study highlights the increasing complexity of FPGA designs driven by factors such as embedded processors, asynchronous clock domains, and stringent security and saf... » read more

AI Agents For UVM Generation: Challenges And Opportunities
By Kexun Zhang - 25 Sep, 2025 - Comments: 0

By Yuheng Tang and Kexun Zhang In the last two years, the role of AI tools in developers' workflows has rapidly expanded. What were once simple "code completion" engines have since evolved into agents that can read documentation, test their own code, and improve via self-reflection. While AI has already begun enhancing RTL design workflows, its exploration in verification remains in early st... » read more

The Future Of Verification
By Brian Bailey - 24 Sep, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

New Demands For IP Reuse
By Brian Bailey - 17 Sep, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight;... » read more

From Discovery To High-Speed Delivery: A Unified Verification Approach For UCIe 3.0 Features And Manageability
By Ujjwal Negi - 11 Sep, 2025 - Comments: 0

By Ujjwal Negi and Prashant Dixit The Universal Chiplet Interconnect Express (UCIe) standard is redefining multi-die integration, enabling high-performance, scalable connections between heterogeneous chiplets. UCIe 2.0 introduced a dedicated manageability layer — a control plane for configuring, monitoring, and coordinating chiplet management elements independently from mainband and sideba... » read more

The Demise Of Static Timing Verification?
By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

Verifying The Evolving UCIe Landscape
By Siemens EDA - 10 Sep, 2025 - Comments: 0

This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One Avery VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table setup for both direct an... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 28 Aug, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy