tag: verification

Formally Modeling A Security Monitor For Virtual Machine-Based Confidential Computing Systems (IBM)
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “Towards a Formally Verified Security Monitor for VM-based Confidential Computing” was published by researchers at IBM Research and IBM T.J. Watson Research Center. Abstract: "Confidential computing is a key technology for isolating high-assurance applications from the large amounts of untrusted code typical in modern systems. Existing confidential computing syste... » read more

New Concepts Required For Security Verification
By Brian Bailey - 28 Aug, 2023 - Comments: 0

Verification for security requires new practices in both the development and verification flows, but tools and methodologies to enable this are rudimentary today. Flows are becoming more complex, especially when they span multiple development groups. Security is special in that it is pervasive throughout the development process, requiring both positive and negative verification. Positive ver... » read more

Optimizing IC Designs For Real-World Use Cases
By Brian Bailey - 24 Aug, 2023 - Comments: 0

Semiconductor systems are becoming more focused on power, performance, and area for the primary scenarios they are likely to see in real-world applications, but increasingly at the expense of secondary tasks. This is happening at all levels of abstraction and all stages of the design flow. At the highest level, processors are being optimized to run a given set of software. RISC-V is one of t... » read more

AI, Rising Chip Complexity Complicate Prototyping
By Karen Heyman - 24 Aug, 2023 - Comments: 0

Prototyping, an essential technology for designing complex chips in tight market windows, is becoming significantly more challenging for the growing number of designs that include AI/ML. Prototyping remains one of the foundational pillars of the whole shift left movement, allowing software to be developed and tested before actual silicon is available. That, in turn, enables multiple teams t... » read more

The Four Foundational Pillars Of Calibre Shift Left Solutions For IC Design And Implementation Flows
By Siemens EDA - 23 Aug, 2023 - Comments: 0

As the semiconductor industry approaches a new era of digital transformation, design companies everywhere are turning to shift left strategies to address challenges that reduce design cycles while maximizing productivity, optimizing resource efficiency, ensuring design quality, and accelerating time to market. To overcome these challenges in IC design, Calibre shift left technologies include to... » read more

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

New Technology Accelerates Multi-Die System Simulation
By Taruna Reddy - 27 Jul, 2023 - Comments: 0

AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

Using AI To Close Coverage Gaps
By Ed Sperling - 26 Jul, 2023 - Comments: 0

Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

Ditch The Glitch
By Ramsay Allen - 11 Jul, 2023 - Comments: 0

To support the ever-growing performance demands of cutting-edge applications like automotive and hyperscaler, SoC complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To keep up with these demands, design-for-test (DFT) logic must also evolve to ensure greater levels of test robustness and silicon health. The “Shift left” concept which... » read more

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