Week In Review: Manufacturing, Test

By Mark LaPedus - 05 Mar, 2021 - Comments: 0

Government policy The National Security Commission on Artificial Intelligence (NSCAI) this week submitted its final report to Congress and the President. The goal is to develop a national strategy to maintain America’s AI advantages related to national security. As part of the long and complex report, the NSCAI came to a sobering conclusion: “The U.S. government is not prepared to defend t... » read more

Week In Review: Design, Low Power

By Jesse Allen - 05 Mar, 2021 - Comments: 0

Tools Synopsys introduced Euclide, a next-generation hardware description language (HDL)-aware integrated development environment (IDE). Euclide aims to enable earlier detection of bugs and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and UVM development. It assists correct-by-construction code development th... » read more

Week In Review: Design, Low Power

By Jesse Allen - 08 Jan, 2021 - Comments: 1

FPGA and eFPGA company Achronix is going public on Nasdaq via a merger with special-purpose acquisition company ACE Convergence Acquisition Corp. (Nasdaq: ACEV). Upon closing of the transaction, the combined operating entity retain the name Achronix Semiconductor Corporation and will be listed under the ticker symbol ACHX. According to Achronix, the transaction reflects an implied equity value ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Week In Review: Design, Low Power

By Jesse Allen - 07 Jun, 2019 - Comments: 0

M&A Infineon Technologies will acquire Cypress Semiconductor for $23.85 per share in cash, or $10.1 billion. The deal will place Infineon as the number eight chip manufacturer in the world based on 2018 revenues and create an automotive powerhouse, making the combined company the largest supplier of chips to the automotive market. Infineon sees potential to reach into new industrial and co... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 24 May, 2019 - Comments: 0

Internet of Things The Wing unit of Alphabet this summer will begin making drone deliveries in the Vuosarri district of Helsinki, Finland. The unmanned aerial vehicles will bear food and other items from Herkku Food, a gourmet market, and the Café Monami restaurant. The drones will bear deliveries of up to 3.3 pounds over distances of up to 6.2 miles. Comcast is reportedly developing an in... » read more

Week In Review: Design, Low Power

By Jesse Allen - 24 May, 2019 - Comments: 0

M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Week In Review: Design, Low Power

By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Week In Review: Design, Low Power

By Jesse Allen - 10 May, 2019 - Comments: 0

Tools & IP Cadence uncorked the latest version of JasperGold formal verification platform, providing improvements to the proof-solver algorithm and orchestration by using machine learning to select and parameterize solvers to enable faster first-time proofs and optimize successive runs for regression testing. Additionally, it increases design compilation capacity by over 2x with 50% reduct... » read more

Week In Review: Design, Low Power

By Jesse Allen - 12 Apr, 2019 - Comments: 0

IP Flex Logix debuted its new InferX X1 edge inference co-processor, which incorporates the interconnect technology from its eFPGAs and its inference-optimized nnMAX clusters. The chip focuses on high throughput in edge applications with a single DRAM and is optimized for small batch sizes in edge applications where there is typically only one camera/sensor. InferX X1 will be available as chip... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Wave Computing

Week In Review: Manufacturing, Test

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week in Review: IoT, Security, Auto

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power