The Bumpy Road To 3D NAND

The NAND flash memory market is dynamic, but it’s also sometimes predictable. Suppliers tend to roll out identical NAND flash chips and then scale them to smaller geometries. And NAND chip prices rise and fall, depending on the supply/demand equation at a given point.

Going forward, though, the NAND market is expected to become less predictable, if not chaotic, amid a new and major technology transition. Planar NAND scaling is slowing and will soon hit the wall. Realizing that NAND is on its last legs, some vendors are racing each other to ship the next-generation technology—3D NAND. In simple terms, 3D NAND resembles a skyscraper, in which horizontal layers are stacked and then connected using vertical pillars or channels.

Last year, Samsung rolled out the industry’s first 3D NAND device, a 24 layer, 128 Gbit chip. In 2014, Micron and SK Hynix will follow suit. But in contrast, the SanDisk/Toshiba duo won’t ship 3D NAND until 2016. Until then, SanDisk and Toshiba plan to extend planar NAND, saying that 2D technology is cheaper, and provides better performance, than 3D NAND.

The rhetoric will likely create some confusion in the market. So, what’s the reality in NAND? Simply put, today’s 2D NAND will remain the dominant technology, and the most cost-effective, for some time. 3D NAND isn’t expected to reach the crossover point—or the price-per-bit parity level—with 2D NAND until 2015 or 2016, said Greg Wong, an analyst with Forward Insights.

In fact, the transition to 3D NAND could be a long and bumpy road. “3D NAND is a new technology,” Wong said. “So, it may take some time to ramp up the yields. And since all the suppliers have a different timeframe for the introduction of 3D NAND, the issue of when it will become cost-effective will be different for each supplier.”

Initially, 3D NAND is geared for the low-volume solid-state drives (SSD) market. “3D NAND has higher endurance than current-generation 2D NAND technology, which makes it better for enterprise SSD applications,” said Monika Garg, an analyst with Pacific Crest Securities. “But enterprise SSDs consume less than 5% of NAND bits per our estimates. This makes us believe that 3D NAND capacity additions could be limited in 2014.”

Running out of gas
So for now, 2D NAND will remain the mainstream technology. Thanks to 193nm immersion lithography and self-aligned double patterning, NAND vendors have scaled their planar devices to 20nm and below. Today, Micron is shipping the world’s most advanced NAND flash device—a 16nm part.

Still, vendors are struggling to scale the critical element in a device—the floating gate. At the 1xnm node, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And there is an increase in the cell-to-cell interference in the word lines.

All told, planar NAND will supposedly hit the wall at around 10nm. In 2D NAND, the transistor has two gates, which are generally on top of each other. The top one is the control gate. The bottom one is the floating gate. The floating gate is based on doped polycrystalline silicon.

Instead of a traditional floating gate, 3D NAND will make use of a charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory. Today, NOR flash vendor Spansion is the only company that has put charge-trap into mass production, but the rest of the industry has struggled with the technology. “The cause of these difficulties, whatever it may be, may delay the introduction of 3D NAND,” said Jim Handy, an analyst with Objective Analysis, in a blog.

Still, Samsung has managed to ship its initial 3D NAND part based on charge-trap. Built around 30nm to 40nm geometries, Samsung’s so-called V-NAND device also consists of 24 layers and 2.5 million channels in a tiny form factor. “Compared to 20nm planar, (3D NAND) is two times the density and write speeds,” said E.S. Jung, executive vice present of semiconductor R&D at Samsung. “It’s half the power consumption and 10 times the endurance.”

On the other hand, the chip is still not cost-competitive as compared to 2D NAND. “Mass production for Samsung’s 3D NAND device will begin in 2014,” said Alan Niebel, president of Web-Feet Research. “At 24 layers, Samsung’s early 3D NAND device is not economical. So, it will take another generation before it will meet cost parity to planar NAND, probably in late 2014 or 2015.”

3D NAND will approach cost parity when the devices incorporate 32 layers or more, said Bradley Howard, vice president of the Etch Advanced Technology unit at Applied Materials. “Planar NAND isn’t going to stand still in terms of cost per bit. It’s going to move forward,” Howard said. “You have to project where that cost will be in relation to 3D NAND. It’s somewhere at 32 or 48 layers.”

Needless to say, the 3D NAND market is still in its infancy. “A lot of the basics of the structures have been worked out. Now, the focus is on device reliability and how you really fine tune the materials for true high-volume manufacturing,” Howard said.

How to make 3D NAND
Getting 3D NAND into volume production is easier said than done. Planar NAND involves a process of manufacturing horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.

In contrast, the 3D NAND flow involves stacking alternating layers of materials on top of each other. “It’s something like a layer cake with alternating layers of cake and frosting,” said Objective Analysis’ Handy.

The formation of the layers is dependent on two fab technologies—deposition and etch. 3D NAND will require alternating stack deposition. And it also brings three new etch technologies to the mix—high-aspect ratio memory hole etch; high-aspect ratio trench-line etch; and staircase etch.

“Previously, the gating item for 2D NAND was having advanced lithography ready for the next node,” Applied’s Howard said. “Current 193nm immersion will do just fine for 3D NAND. The thing that will reduce the cost-per-bit is not lithography, but rather it is really driven by deposition and etch.”

In the basic 3D NAND process flow, the first step is to build a CMOS logic layer, which serves as the foundation. Then, in some 3D NAND devices, alternating layers of silicon dioxide and polysilicon are deposited on top of the logic. Silicon dioxide serves as the insulator, while polysilicon is used for wordlines and control gates. “What are the challenges for deposition? Depositions are transitioning from single layer to multi-layer stacks. The key there is you really need to have precise control and low defectivity,” Applied’s Howard said.

Alternating stack deposition determines the number of layers for a given device. Following that step, holes are patterned on the top layer. Then, using an etcher, high-aspect ratio trenches are etched from the top of the device to the substrate. “That process is definitely not easy,” Howard said. “It’s not just the aspect ratios, but it’s also how deep we have to go. If you take typical planar NAND, you are looking at 12:1 or 15:1 contacts. In 3D NAND, you are looking at the 40:1 to 60:1 high-aspect ratios.”

Then, the charge-trap and the channels are formed within the device. “What you are doing is drilling holes with contacts to make a channel conductor from top to bottom. Then, you fill that in with a conductor. So in effect, you not only have wordlines, but a vertical stack of wordlines,” he said.

The next big challenge is to connect the peripheral logic to the control gates. Using an etcher, the idea is to etch a staircase pattern into the side of the device. “What we do is print a large patch of resist. And then, we etch through a dielectric layer and a conductor layer. And we pull the resist back and we etch again. Then, you keep doing this multiple times and you have a staircase-like structure,” he said.

Once the 3D NAND devices are manufactured, the chips must undergo a set of rigorous process control steps. 3D NAND vendors will likely overcome many of the challenges and bring the technology into the mainstream. “Everyone is admitting there is an end to planar,” he said. “It’s just a matter of time before 3D NAND will make that crossover.”

Still to be seen, however, is how long 3D NAND will scale. It’s unclear how many layers can be stacked and at what densities. Clearly, though, the migration from 2D to 3D NAND is expected to be a long, and unpredictable, process for chip akers and OEMs a