tag: V-NAND

Monitor Etch Defects on Dies in the Outer Regions Of The Wafer Using ISR
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A technical paper titled "Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning" was published by researchers at Samsung Electronics. Abstract: "We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nan... » read more

Chip Industry Week In Review
By The SE Staff - 13 Sep, 2024 - Comments: 0

Infineon rolled out the world's first 300mm gallium nitride (GaN) wafer, opening the door for high-volume manufacturing of GaN-based power semiconductors. A 300mm wafer contains 2.3 times as many chips per wafer as a 200mm wafer. Fig.1: Infineon's 300mm GaN wafer. Source: Infineon The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report th... » read more

Is There A Limit To The Number of Layers In 3D-NAND?
By Karen Heyman - 24 Aug, 2022 - Comments: 1

Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

Inside Inspection And Metrology
By Mark LaPedus - 18 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about inspection, metrology and other issues with Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. What follows are excerpts of that conversation. SE: Today, the industry is working on a new range of complex architectures, such as 3D NAND and finFETs. For these technologies, the industry is clearly struggling... » read more

Flash Dance For Inspection And Metrology
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

3D NAND Market Heats Up
By Mark LaPedus - 19 Feb, 2015 - Comments: 4

After some delays and uncertainty in past years, the 3D NAND market is finally heating up. In 2013 and 2014, Samsung was the only vendor participating in the 3D NAND market. Most other suppliers were supposed to ship 3D NAND devices in volumes last year, but vendors pushed out their production dates for various business and technical reasons. Going into 2015, [getentity id="22865" e_nam... » read more

The Bumpy Road To 3D NAND
By Mark LaPedus - 23 Jan, 2014 - Comments: 1

The NAND flash memory market is dynamic, but it’s also sometimes predictable. Suppliers tend to roll out identical NAND flash chips and then scale them to smaller geometries. And NAND chip prices rise and fall, depending on the supply/demand equation at a given point. Going forward, though, the NAND market is expected to become less predictable, if not chaotic, amid a new and major technol... » read more

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