The Week In Review: Design

IP
ARM introduced a new software platform and a free operating system aimed at IoT development. The OS incorporates security, communication and device management features for improved energy efficiency. The device server simplifies the connection and management of devices, incorporating security and improving efficiency.

Cadence rolled out a broad IP portfolio for TSMC‘s 16nm platform, and tools and IP to support the foundry’s ultra-low-power technology platform.

Tools
Synopsys beefed up the Liberty library format, incorporating on-chip variation extensions to speed up timing closure. The new feature set was ratified by the Liberty Technical Advisory Board on Aug. 1.  Synopsys’ Coverity unit also launched a free beta version of a tool to detect defects in Java code.

Arteris rolled out a fault-tolerant feature for its NoC technology, including redundant unit checkers and a fault safety controller, BiST for resilience functions and data packet integrity checkers. The technology is aimed at automotive, industrial and aerospace/defense markets.

ARM unveiled two tools to simplify finFET designs, including one tool to optimize SoC power grid layouts and another to improve the accuracy of managing on-chip variation. The power grid tool eliminates the need to apply detailed finFET design rules, according to the company.

Open-Silicon joined Carbon Design Systems‘ portal for pre-built virtual prototype systems and subsystems. Open-Silicon contributed several of those systems/subsystems, which include software, IP and system solutions from multiple vendors.

Deals
Mentor Graphics teamed up with AMD to create a network functions virtualization solution, creating building blocks out of virtualized classes of network node functions. The solution is built on a 64-bit ARM processor. Mentor also has begun collaborating with TSMC on 10nm tools.

ARM and Cadence expanded their collaboration agreement for IoT and wearable applications for TSMC’s ultra-low power technology process at 55nm, 40nm and 28nm.

TSMC is collaborating with Synopsys on a 16nm finFET custom design reference flow. The flow improves parasitic-aware circuit simulation and adds other features for faster analog layout with finFETs. The foundry also is working with Synopsys on 10nm and has certified Synopsys’ tools for 16nm finFET+.

Sonics won a deal with Israel’s SatixFy, which will use Sonics’ NoC technology to improve IP core integration. SatixFy makes chips for broadband satellite communications, aka high-throughput satellite or HTS.

Chips
Rambus‘ Cryptography Research Division unveiled a suite of cryptographic cores that are resistant to differential power analysis, including 128-bit and 256-bit versions that include algorithms such as 3DES, ECC, SHA and Suite B.

NXP uncorked a new family of microcontrollers based on ARM’s Cortex M0+, aimed at IoT sensor-dense designs. The MCUs are aimed at everything from building automation and lighting controls to server and rack monitors and wearable electronics.

ARM and TSMC introduced a roadmap for 10nm 64-bit ARM-based processors.

Atmel introduced a new family of MCUs aimed at IoT, industrial and automotive markets. The chips, which are based on ARM’s core, will come in three flavors: general purpose, connectivity and automotive.  Atmel also inked a deal with ARM for its IoT development platform.

HP rolled out its first 64-bit ARM-based servers, which it plans to market as highly efficient, high-performance hardware aimed at specific workloads.

Events Next Week
Atrenta will hold its first user conference on Oct. 8 at Levi’s Stadium in Santa Clara.

The EDA Consortium will host an emerging companies series on Oct. 8, featuring a presentation by former Jasper CEO Kathryn Kranen and Jim Hogan.