Warp Speed Ahead

The computing world is on a tear, but not just in one direction. While battery-powered applications are focused on extending the time between charges or battery replacements, there is a whole separate and growing market for massive improvements in speed.

Ultimately, this is where quantum computing will play a role, probably sometime in the late 2020/early 2030 timeframe, according to multiple industry estimates. Still, although there has been some progress in room-temperature quantum computing, the bulk of that computing initially will be done in extreme cold inside of data centers.

Between these two extremes, there is a growing focus on new architectures, packaging, materials and ever-increasing density to deal with massive amounts of data.

“If you look at anything around big data, all of these systems will become smarter and smarter,” noted Synopsys chairman and co-CEO Aart de Geus. “Over time the desire is not to get 2X performance, but 100X. The only way to get there is not by using faster chips, but by using chips that can only do a single task. In other words, algorithm-specific. By simplifying the problem, you can make things much more efficient.”

And this is where computing is about to take a big leap. In the past, the focus was on how to get more speed out of general-purpose processors, whether those were CPUs, GPUs or MCUs. Increasingly, processors are being designed for specific tasks. Rather than just one processor with many cores, there are multiple processors—some with just a single core, some with multiple cores—to handle very specific tasks and very specific data types.

This puts new pressure on big chipmakers. Instead of spending years developing the next rev of a general processor, the future increasingly is about flexibility, choice, and an increasing level of customization. This is why Intel bought Altera, and it helps explains why all processor makers have been ramping up the number of chips they offer. The risk of not coming up with so many possible options is that companies begin architecting their own chips, which is already happening. Apple, Amazon, Google, Microsoft, Facebook and Samsung today are creating chips for specific applications. It’s also why there is so much attention being focused on programmability and parallelism, whether that involves embedded FPGAs, DSPs, or hybrid chips that add some level of programmability into ASICs.

It also puts pressure on chipmakers to come up with new approaches for improving performance. Just turning up the clock speed is becoming more difficult at advanced nodes due to thermal limitations, which is why companies such as Cisco and Huawei began using 2.5D architectures to improve throughput between components. Interest in advanced packaging based on interposers, TSVs and lower-cost bridges continues to grow, along with more cache coherency to limit the amount of data that needs to be pushed back and forth between memory and the processor. There is even a resurgent interest in moving some processing into memory. And across the board, there is a growing emphasis on software-defined hardware, where the hardware and software are developed together much more closely than in the past.

So what can you actually do with 100X improvement in performance? Or how about 1,000X improvement? The answer isn’t entirely clear yet, but it does open up vast new possibilities that bode well for semiconductor design for many years to come.