Week In Review: Design, Low Power

Perforce Software acquired Methodics. Founded in 2006 and based in San Francisco, Methodics’ IP lifecycle management and traceability software will join Perforce’s larger portfolio of DevOps software that includes version control, Agile planning, and static code analysis. The two companies have had a strategic partnership in place with customers using software from both companies. Terms of the deal were not disclosed.

Tools & IP
Mentor introduced Analog FastSPICE eXTreme for nanometer-scale verification of large, post-layout analog designs. Features include resistor-capacitor circuit reduction algorithms, significant performance improvements to the Analog FastSPICE core SPICE matrix solver, and full-spectrum device noise analysis capabilities designed to enable silicon-accurate simulation. Initial benchmarks show 10X simulation performance over the previous generation.

Aldec added a RISC-V focused static verification rule set to its ALINT-PRO verification tool. The rule set includes coding styles, data types and operations, coding for implementation, and SystemVerilog constructs that together verify correct use of constraints and variables, data types usage in expressions, as well as checks for optimal synthesis and timing closure.

Codasip debuted the official release of Bk7, a Linux-capable RISC-V core that targets customization and domain-specific optimization. Bk7 is a 64-bit processor core with a single in-order 7-stage pipeline, compliant with the RV64IMAFDC ISA.

Mentor expanded Calibre Recon to the nmLVS circuit verification platform to analyze IC designs for errors during early-stage verification design iterations. Calibre nmLVS-Recon is based on a flexible configuration framework that enables multiple use models and features automated, intelligent execution heuristics as well as options for data partitioning, design breakdown, data reuse, task distribution, and error management.

Flex Logix added emulation models for its EFLX eFPGA and nnMAX AI Inference IP for use on Mentor’s Veloce Strato emulation platform. The models have been proven in the verification of Flex Logic’s own SoC, InferX X1, which are now in fab.  InferX X1 has a 2×2 nnMAX array and 1×1 EFLX eFPGA.

SiFive updated its portfolio of RISC-V Core IP with the 20G1 release. The release improves the capabilities of a range of IP including 2.8x higher performance in memory-intensive workloads running on a U7-Series, 25% lower power for the U74 processor, and 11% area reduction of the E3-Series on 28nm.

PLDA teamed up with Aldec, Avery Design Systems, and Mentor to offer a Robust Verification Toolset that includes verification IP covering standards compliance for PCIe, AMBA AXI, CXL, CCIX and Gen-Z; simulators for mixed-language designs with UVM testbenches; and synthesis and static verification tools.

Mobile Semiconductor announced a new generation of Ultra Low Leakage (ULL) and Ultra Low Power (ULP) SRAM Memory Compilers on GlobalFoundries’ 22FDX process. The memory compilers target edge AI chips with an improved performance to power ratio and leakage in the nano-amp range.

Deals & Certifications
Graphcore used Synopsys’ VCS simulation solution with Verdi debug to verify its recently announced Colossus GC200 Intelligence Processing Unit (IPU), which features 59.4Bn transistors and 1,472 independent processor cores. Graphcore cited reduced regression turnaround time and productivity boost on large designs.

Cadence’s millimeter wave (mmWave) reference flow was certified for UMC’s 28HPC+ process technology. The flow, based on  Virtuoso RF solution, incorporates schematic capture, layout implementation, parasitic extraction, EM analysis and RF circuit simulation, integrated LVS and DRC in a single flow.

Aldec and SmartDV inked an agreement to link SmartDV’s Verification IP with Aldec’s Riviera-PRO high-performance simulation and debugging tool. The two companies will work to ensure the VIP and simulator work together and jointly market solutions.

BMW Group is using Ansys’ LS-DYNA for passive safety system development, such as seatbelt restraints and air bags, and support for virtual crash testing in the next generation of vehicles.

Standards
CHIPS Alliance released the Advanced Interface Bus (AIB) version 2.0 draft specification on GitHub. The AIB standard is an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. AIB 2.0 has more than six times the edge bandwidth density of AIB 1.0 through increases in the per-wire line rate and the number of IOs per channel.

Numbers
Cadence reported financial results for the second quarter of 2020 with revenue of $638 million, up 10% compared to the second quarter last year. On a GAAP basis, income for Q2 20202 was $0.47 per share, up 23.7% compared to $0.38 per share in Q2 2019. Non-GAAP income per share was $0.66, up 15.8% from $0.57 in the same quarter last year. Design activity remains strong, noted Cadence CEO Lip-Bu Tan. “To ensure business continuity, we are further investing in infrastructure and collaboration platforms to maintain high levels of productivity and innovation.” Cadence CFO John Wall said the company is raising outlook for the year to 11% revenue growth and 33% non-GAAP operating margin.

Videos of the week:
3 Types Of AI Hardware
All AI chips are not the same, but there are commonalities.
Ins And Outs Of In-Circuit Monitoring
Techniques to predict failures and improve reliability.
EFPGAs Vs. FPGA Chiplets
Which approach works best where.