Week In Review: Design, Low Power

Tools & IP
Synopsys is joining Microsoft in the U.S. Department of Defense’s Rapid Assured Microelectronics Prototypes (RAMP) program to support the development of IC hardware and workflow prototypes that incorporate Synopsys’ assured design and manufacturing flows into Microsoft Azure. The RAMP program aims to bring commercial capabilities and speed to the development of semiconductors for government systems. Another goal is developing security at all phases of a system’s life.

Pulsic debuted a new tool that provides detailed visualizations and accurate area estimations of analog circuits. Animate Preview recognizes common analog circuit topologies and places devices to achieve matching symmetry and optimal flow of the critical paths in the circuit, obeying DRC and process rules. Physical previews are generated when a schematic is loaded and each time the schematic is updated. The tool is available under a freemium model.

AnalogX uncorked 7nm and 6nm SerDes IP that is silicon-proven and focused on low power and latency. The company also recently expanded.

Deals
Flex Logix and Synapse Design Automation said they taped out an ASIC for a mutual customer using the EFLX eFPGA IP ported to a new process in less than a year. Flex Logix noted it was able to provide the customer with early IP drops that allowed them to co-develop the ASIC while porting to a new process node.

Socionext implemented Arteris IP’s FlexNoC interconnect IP and the accompanying Resilience Package in multiple automotive chips, including an automotive SoC fabricated using 5nm process technology. The chips will be used in applications including ADAS and autonomous driving systems. Socionext cited the ability to see early in the design process the layout impacts of SoC and NoC architecture choices and to tailor safety mechanisms for the desired ISO 26262 ASIL.

Fujitsu will use Xilinx’s UltraScale+ technology for its O-RAN 5G radio units to be deployed in the first O-RAN-compliant 5G greenfield networks in the U.S. Fujitsu is also evaluating Xilinx RFSoC technology to further reduce cost and power consumption for additional future site deployments.

Quantum computing
IBM revealed its quantum computing development roadmap targeting improvements the company says will lead to a 100x speedup in workloads that exploit iterative circuit execution. A key focus is the Qiskit runtime execution environment that increases capacity to run circuits and ability to store quantum programs. In the coming years, IBM plans to allow quantum kernel developers to run dynamic circuits and debut circuit libraries and advanced control systems for manipulating large qubit fabrics.

As part of a collaboration, the University of Sydney and Microsoft developed a single chip that can generate control signals for thousands of qubits. The researchers note that currently, the world’s largest quantum computers use about 50 qubits, a number that will need to be increased to thousands or millions to recognize the technology’s potential.

“Current machines create a beautiful array of wires to control the signals; they look like an inverted gilded birds’ nest or chandelier. They’re pretty, but fundamentally impractical. It means we can’t scale the machines up to perform useful calculations. There is a real input-output bottleneck,” said Professor David Reilly, a designer of the chip who holds a joint position with Microsoft and the University of Sydney.

Dr Kushal Das, a joint inventor of the chip and senior hardware engineer at Microsoft, said, “Our device does away with all those cables. With just two wires carrying information as input, it can generate control signals for thousands of qubits.” Key to the chip is its ability to operate at cryogenic temperatures, allowing it to operate in close proximity to the qubits.

Infineon teamed up with five research institutes in Germany, the Walther Meißner Institute, the Karlsruhe Institute of Technology, the Friedrich Alexander University of Erlangen-Nuremberg, the Forschungszentrum Jülich, and the Fraunhofer Institute for Applied Solid State Physics, on the “German Quantum Computer based on Superconducting Qubits” (GeQCoS) project. With funding of €14.5 million (~$17.4M), the project aims to develop a quantum processor based on superconducting qubits and demonstrate it on a prototype within four years. “Quantum computing has reached the point where we now need to translate the science into practical application,” said Sebastian Luber, Senior Director Technology & Innovation at Infineon. “This, however, requires improvements to the features of quantum processors, and it must become possible to manufacture them on an industrial scale. The trick is to move forward, even if it is not yet clear which technology is best suited.”

Meanwhile, The Quantum Daily considers what the appointment of Andy Jassy, former AWS head, as CEO of Amazon means for the company’s future development of quantum computing services.

Numbers & People
Rambus reported financial results for the fourth quarter of 2020 with revenue of $61.9 million, up 3.3% from the same quarter last year. On a GAAP basis, there was a loss per share of $0.11, compared to $0.09 per share loss in Q4 2019. For the full year 2020, revenue was $242.7 million, up 8.3% from 2019. On a GAAP basis, the company saw a loss per share of $0.39 in 2020, compared to a loss per share of $0.81 in 2019. Rambus noted that it saw record annual product revenue of $114.0 million driven by Memory Interface Chips, which were up 56% year over year.

The ESD Alliance and IEEE CEDA announced the Phil Kaufman Hall of Fame, and award to posthumously recognize individuals who made significant and noteworthy contributions through creativity, entrepreneurism, and innovation to the electronic system design industry and were not recipients of the Phil Kaufman Award.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The 2021 International Solid-State Circuits Virtual Conference will be held Feb. 13-22. The International Symposium on Field-Programmable Gate Arrays will take place Feb. 28-Mar. 2.

In March, DVCon 2021 will be held Mar. 1-4. The U.S. government-focused electronics conference GOMACTech will be held Mar. 29-Apr. 1.