Week In Review: Design, Low Power

Tools
Cadence’s digital and custom/analog flows were certified for TSMC’s N3 and N4 process technologies. Updates for the digital flow includes efficient processing of large libraries, additional accuracy during library cell characterization and static timing analysis, and support for accurate leakage calculation required in N3 and static power calculation for new N3 cells.

Synopsys’ digital and custom design platforms have been certified for TSMC’s 3N and 4N process technologies. The Synopsys flow has been updated for faster timing closure, full-flow correlation from synthesis to place-and-route to timing, as well as physical signoff. It includes improved synthesis and global placer engines that optimize library cell selection and placement results as well as using new footprint optimization algorithms.

Additionally, Synopsys’ 3DIC Compiler platform provides access to TSMC 3DFabric-based design methodologies. These methodologies deliver 3D chip-stacking support in the System-on-Integrated-Chips (TSMC-SoIC) technology and 2.5/3D advanced packaging support in Integrated Fan-Out (InFO) and Chip-on-Wafer-on-Substrate (CoWoS) technologies.

Arm used Siemens Digital Industries Software’s Solido Variation Designer software to verify its standard cell IP. Arm said it improved IP validation runtime by 1,000X compared to traditional brute force statistical methods, and that by migrating its Solido Variation Designer usage to Arm-based Graviton2 processors on AWS, it was able to further reduce compute costs by 24% and total CPU time by 12%, as well as improve turnaround time by 6%.

IP
Cadence demonstrated its PCIe 6.0 IP on TSMC’s N5 process. The IP consists of a high-performance DSP-based PHY and a companion controller. The company said the PAM4/NRZ dual-mode transmitter delivered optimal signal integrity, symmetry and linearity with extremely low jitter, while the DSP-based receiver demonstrated data recovery capabilities while withstanding harsh signal impairments and channel loss in excess of 35dB at 64GT/s.

Eyenix licensed Arteris IP’s FlexNoC interconnect IP for its next-generation image processing SoC. The NoC interconnect IP will be the dataflow backbone for image signal processors providing enhanced sensitivity and high-resolution HD imaging through a low current, low power single-chip solution for the security/surveillance market.

Omni Design uncorked silicon-validated 12-bit 6 Gsps ADC and 12-bit 7 Gsps DAC converters on TSMC’s 16nm process. The DAC includes versions with 14/12/10 bits of resolution and 8/4/2 GHz update rates and includes two-tone direct digital synthesizer (DDS) and return-to-zero (RZ) signaling capabilities as built-in options.

eTopus Technology introduced a 400G Long Range (LR) IP solution incorporating Forward Error Correction (FEC) IP and the eTopus DSP-based SerDes PHY (ePHY) IP with a combined latency of sub 10ns. The high-speed transceiver architecture supports a wide range of data rates for multiple standards, such as Ethernet, OIF CEI-112G, PCI-SIG PCIe Gen 1 through 6, and insertion loss from few to above 30dB.

AI
Flex Logix announced production availability of its InferX X1P1 PCIe accelerator board. Using a dynamic TPU array architecture, the InferX X1 is designed around low latency processing of Batch=1 workloads with a special focus on edge vision applications. A software toolkit to support customer model porting is also available.

Memory
SK Hynix has developed an HBM3 product, the latest version of the high-bandwidth memory standard that stacks multiple DRAM chips. It can process up to 819GB per second and will be provided in two capacity types of 24GB and 16GB with built-in on-die error-correction code.

NSCore introduced its One-Time Programmable Plus (OTP+) non-volatile memory. The OTP+ is able to be re-programmed to address the potential changes in software late in the product development process. It uses NSCore’s “P-Channel Schottky Cell” bit-cell structure that the company says requires no additional process steps with power performance of 1uA/MHz. It targets energy harvesting chips working in the 2.4 GHz Bluetooth Band for IoT applications.

Safety
Cadence debuted the Cadence Safety Solution, which provides integrated analog and digital safety flows and engines for FMEDA-driven verification and ISO 26262 and IEC 61508 certification. It targets safety-critical automotive, industrial, and aerospace applications. It includes failure modes, effects, and diagnostic analysis management, fault simulation, formal verification, and automated safety mechanism insertion.

Razorcat Developments integrated Imperas’ Arm processor reference models and virtual platforms into the TESSY environment for embedded software testing. TESSY provides automatic regression testing and software maintenance for safety critical embedded applications such as automotive, industrial control, medical, and aeronautics.

HPC
Ansys’ LS-DYNA structural simulation software now supports Fujitsu’s 64-bit Arm-based supercomputers PRIMEHPC FX1000 and FX700. The companies promote the solution as a way to reduce HPC energy consumption and costs by offloading CAE to more energy-efficient supercomputers.

IoT
Arm unveiled Arm Total Solutions for IoT, which aims to simplify and modernize software development for IoT devices. It includes hardware IP, software, machine learning models, and application specific reference code. It also includes Arm Virtual Hardware Targets, a cloud-based offering that delivers a virtual model of the Corstone subsystem to enable software development using agile methodologies without the need for physical silicon. The first configuration addresses general-purpose compute and ML workload use-cases, including an ML-based keyword recognition example. Virtual Hardware Targets are available for multiple configurations of the Arm Corstone-300 subsystem from SoC partners, incorporating the Cortex-M55 processor and Ethos-U55 microNPU. Arm also announced Project Centauri, which aims to provide a set of device and platform standards and reference implementations for the Cortex-M software ecosystem.

Infineon added software support for the Matter smart home standard. It enables companies using Infineon’s Wi-Fi, Bluetooth, or MCUs to add Matter capability to existing and new products such as smart speakers.

Infineon launched CIRRENT Cloud ID, a service that automates cloud certificate provisioning and IoT device-to-cloud authentication. It targets cloud-connected product companies in the industrial, consumer, healthcare, medical, and manufacturing industries.

IAR Systems announced a solution to speed development and deployment of IoT devices with Microsoft Azure IoT and RTOS platforms. The embedded development toolchain integrates cloud-ready identity and root of trust technology to help develop devices that are uniquely cryptographically identifiable, with secured software installation, edge secure update management, and secured production management.

Wireless
Sivers Semiconductors will acquire MixComm for $135.0 million, a combination of $22.5 million in cash and $112.5 million in shares, with another $20.0M contingent on milestones. Both companies produce 5G mmWave chips, and the acquisition will result in a joint IP portfolio of RFIC/BFIC (radio frequency/beam forming IC) chipsets in a variety of mmWave technologies, including SiGe and RF-SOI. It covers mmWave use cases such as unlicensed 5G, licensed 5G infrastructure, fixed wireless access customer premises equipment, and satellite communications. Sivers will also gain MixCom’s Antenna-in-Package technology. The deal is expected to close by mid-Q1 2022. Founded in 2017, MixComm is headquartered in Chatham, New Jersey.

Navitas Semiconductor went public on Nasdaq under the ticker NVTS. The company produces GaN power ICs targeted for the mobile charger market, and it plans to expand into the consumer, solar, energy storage, data center and EV markets. The listing was the result of Navitas’ merger with SPAC Live Oak II in a deal that raised approximately $400 million.

Automotive
Electro Magnetic Applications (EMA) and Ansys introduced EMA3D Charge, a simulation solution for predicting the effects of electrical charging and discharging phenomena and determining how electrical components may be harmed. The product combines CAD import, design and simplification, simulation setup and meshing, and result generalization and visualization in one solver technology. Target areas include electronics for aerospace and automotive.

Ford used Ansys’ optical simulation software in development of its predictive smart headlights before hardware prototype availability. The headlight system uses real-time location data to direct beams into upcoming turns with the aim of allowing motorists to better see around corners and respond to hazards.