Week In Review: Design, Low Power

By Jesse Allen - 01 Apr, 2022 - Comments: 0

Tools Synopsys introduced a new model for using its EDA tools on the cloud. Synopsys Cloud provides pay-as-you-go access to the company's cloud-optimized design and verification products, with pre-optimized infrastructure on Microsoft Azure to address higher levels of interdependencies in chip development. "As more design flows incorporate AI, requiring even more resources, the virtually unlim... » read more

Week In Review: Design, Low Power

By Jesse Allen - 04 Feb, 2022 - Comments: 0

Tools & IP Ansys updated its product suite, adding new tools and workflows in Ansys 2022 R1. It adds Phi Plus meshing technology to improve simulation of PCB and complex 3D IC packaging. It also introduces RedHawk-SC SigmaDVD, a statistically realistic modeling technique to identify the worst-case dynamic voltage-drop in hours and make it possible to achieve near 100% coverage of all relev... » read more

Week In Review: Design, Low Power

By Jesse Allen - 22 Oct, 2021 - Comments: 0

Tools Cadence's digital and custom/analog flows were certified for TSMC's N3 and N4 process technologies. Updates for the digital flow includes efficient processing of large libraries, additional accuracy during library cell characterization and static timing analysis, and support for accurate leakage calculation required in N3 and static power calculation for new N3 cells. Synopsys' digita... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: eTopus Technology

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power