Week In Review: Design, Low Power

DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing.

Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler

EDA and IP remain strong, approaching $4 billion in Q1, according to SEMI’s ESD Alliance. Revenue remains in the double-digit range, but the underlying fundamentals have shifted from traditional chipmakers to a mix of chipmakers and systems companies designing their own chips for internal use. Likewise, funding for startups in this market continues to pour in from around the globe, particularly for power semis, RISC-V SoCs, photonics, chip design, AI hardware, quantum, and power devices.

Tools

Siemens Digital Industries Software introduced a new cloud-based AI tool for IC design and verification, called Solido Design Environment, and a new tool for Calibre called DesignEnhancer. DesignEnhancer will help deliver “DRC-clean” designs by automatically analyzing and inserting up to 1M or more correct-by-construction vias and interconnects.

Keysight released its latest suite of EDA software tools called PathWave Design 2024. The tools add software automation, design data and IP management, team collaboration, and other development lifecycle capabilities. Keysight also introduced a new source measure unit (SMU) tool with 20 precision channels within a 1U rack space to speed the characterization of IC designs. The PZ2100 Series High-Channel Density Precision SMU requires fewer connections and less testing of multiple ports on a single device-under-test (DUT).

Ansys and Altium launched a bi-directional digital bridge between Altium’s ECAD tool and Ansys’ simulation, which also enables updates and syncing.

Certifications and Deals

Broadcom won approval from the European Commission (EU) to acquire VMware. The $61 billion proposed acquisition is Broadcom’s largest ever and will boost the chipmaker’s portfolio of infrastructure and management software.

Siemens expanded its agreement with AWS with a Strategic Collaboration Agreement (SCA) to focus on their mutual customers who are designing ICs via cloud. Specifically, the two companies are developing Cloud Flight Plans — best-known methods and technologies for running Siemens’ EDA tools in AWS environments.

Intel Foundry Services (IFS) certified several EDA design flows for its Intel 16 Process, including  Synopsys’ AI-driven EDA suite and its foundation and interface IP;  Cadence’s digital and custom/analog flows and its design IP; Ansys’ multiphysics tools for power and signal integrity, and reliability signoff verification; and Siemens EDA’s DFM tools.

Flexium, a printed circuit board (PCB) manufacturer, is using Ansys’ tools to verify 5G mmWave antenna module design on flexible circuits.

NSITEXE, a subsidiary of DENSO, is using Cadence and Imperas tools to verify RISC-V processor IP for functional safety and embedded systems.

Keysight and Skylo signed a memorandum of understanding (MOU) under which Keysight will use Skylo’s test cases to create a certification for 3GPP 5G Release 17 (Rel-17) non-terrestrial networks (NTN) chipsets, modules, and devices using narrowband internet of things (NB-IoT) protocol over NTN.

Research

Researchers at the University of Minnesota synthesized a topological semimetal thin film that can boost performance and lower energy consumption.

Notre Dame University researchers explored the viability of large language models for hardware-software co-design.

Researchers at ETH Zurich and the University of Bologna developed a RISC-V host platform for domain-specific accelerator plug-ins.

Upcoming events

• Rambus Design Summit – July 18-19 (Online)
• 2023 Flash Memory Conference & Expo – August 8-10 (Santa Clara, CA)
• DARPA: Electronics Resurgence Initiative (ERI) – August 22-24 (Seattle, WA)
• Hot Chips 2023 – August 27-29 (Hybrid online & Stanford, CA)
• NVMTS 2023: Non-Volatile Memory Technology Symposium – August 30-September 1 (Leuven, Belgium)
• IEEE International System-on-Chip Conference (SOCC): SoCs/ SiPs for Edge Intelligence & Accelerated Computing – September 5-8 (Santa Clara, CA)
• AI Hardware Summit 2023 – September 12-14 (Santa Clara, CA)
• DVCON India: Design & Verification Conference & Exhibition – September 13-14 (Bangalore, India)
• More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

• Programming Processors In Heterogeneous Architectures
• Power/Performance Costs Of Securing Systems
• EDA’s Role Grows For Preventing And Identifying Failures
• The Uncertainties Of RISC-V Compliance
• Verification And Test Of Safety And Security
• Better Choreography Required For Complex Chips
• CEO Outlook: Chiplets, Data Management, And Reliability

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