Week In Review: Design, Low Power

ON Semiconductor will acquire Quantenna Communications for $24.50 per share in an all cash transaction, representing an equity value of approximately $1.07 billion and enterprise value of approximately $936 million. Quantenna, a maker of Wi-Fi chipsets, was founded in 2006 and went public in late 2016.

Tools & IP
Achronix completed testing and is now demonstrating the 112 Gbps SerDes that will be used in its next-generation FPGAs. The 112 Gbps SerDes is fabricated on TSMC’s 7nm finFET process technology and provides multi-standard support for a range of digital serial communications standards with data rates ranging from 1 Gbps to 112 Gbps. The SerDes’ receivers employ advanced DSP techniques including constant modulus algorithm (CMA) adaptive equalization and decision-based adaptation to deliver the best possible receiver performance at low power.

Wave Computing released the first of its MIPS Open program components. Under the program, participants have full access to the most recent version, R6, of the 32-and-64-bit MIPS architecture free of charge, including extensions such as virtualization, multi-threading, SIMD, DSP and microMIPS code compression. Additionally, registered MIPS Open program participants are licensed under Wave’s existing global patents.

Arm will offer Mentor’s Tessent TestKompress software cell-aware library models as part of the 18.2 and later EDA specifications used for Arm Artisan Physical IP development. Mentor’s Brady Benware says the collaboration will allow mutual customers to immediately start implementing cell-aware test and diagnosis without having to create cell-aware library models themselves.

Codasip uncorked the latest versions of its Codasip Studio and CodeSpace. Version 8.0 introduces a new Codasip Bus Protocol (CPB) and adds integration of LLDB and OpenOCD.

Cortus debuted new RISC-V processors available for customer ASIC designs implemented by Cortus’ IC Design Service. The six available cores range from a low gate count, low power 32 bit CPU core to a high performance 64 bit processor with double precision floating point and MMU.

Deals
Synopsys teamed up with Samsung Foundry to provide a secure, scalable cloud-based IC design and verification environment on the Synopsys Cloud Solution for designers using Samsung Foundry’s process technology. Samsung Foundry says it was able to accelerate the development of its 7nm Ultra-High Density Standard Cell libraries about 30% using Synopsys’ characterization solution on the cloud.

Morningcore Technology licensed Arteris IP’s FlexNoC interconnect IP for use in its next-generation automotive LTE vehicle-to-vehicle/vehicle-to-infrastructure (V2X) communication modems. Morningcore cited bandwidth, latency and power requirements as well as local support as part of the decision.

Air conditioner manufacturer Daikin adopted Mentor’s Xpedition PCB design flow software as its global design environment. Daikin cited the ability to share CAD library and design data across its globally dispersed locations as improving operational efficiency and productivity.

Defense company Northrop Grumman is using Cadence’s system and verification, digital and signoff, custom/analog and packaging tools, as well as IP, in developing advanced-node SoC projects.

Events
Fireside Chat with Paul Cunningham: April 10, 6:30-9:00 p.m. in Milpitas, CA. Jim Hogan and Cadence’s Paul Cunningham will discuss topics from the startup experience, artificial intelligence, concurrent physical optimization to system functional verification and open source architectures. The event is hosted by the ESD Alliance.

Linley Spring Processor Conference 2019: April 10-11 in Santa Clara, CA. Beginning with an overview of the processor and IP market, technologies, equipment-design, and silicon trends, the event will include talks and panel discussions on a range of topics. AI chips and IoT security are both major focuses.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West. Super-early registration ends Mar. 29.