Week In Review: Design, Low Power

M&A
Intel will acquire Barefoot Networks, a maker of programmable Ethernet switch silicon and the P4 networking programming language for data centers. Founded in 2013, the Santa Clara-based company has raised $155.4 million in funding. Terms of the deal were not disclosed, but Intel expects the acquisition to be final in the third quarter of this year.

Tools & IP
Mentor extended its Valor NPI software with an automated PCB design-for-manufacturing flow designed to provide meaningful DFM analysis without having every user be a DFM expert. With the tool, critical design data is automatically extracted to derive PCB technology classifications for appropriate manufacturing process constraints. It works with all major PCB layout tools:  Xpedition and PADS software suites, Cadence Allegro, Zuken Board Designer, and Altium products.

Andes Technology debuted its RISC-V FreeStart program, which makes the company’s N22 RISC-V CPU IP core available to download with no license fee; a royalty is charged for commercial production. The N22 is a small, 2-stage pipeline 32-bit RV32I/EMAC RISC-V CPU core and is integrated with interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform.

Deals & Certifications
ANSYS and BMW are teaming up on a simulation tool chain for developing autonomous vehicle technologies. The multi-year agreement will target BMW’s Level 3 offering and upcoming Level 4-5 technology for the BMW iNEXT, expected to launch in 2021. ANSYS will assume exclusive rights to the simulation tool chain technology for commercialization to a wider market.

Toshiba implemented Cadence’s Tensilica Vision P6 DSPs in its next-generation automotive SoC. Toshiba also integrated the Cadence Xtensa Imaging Library (Xi-Lib) into its SDK, allowing customers to easily access the Vision P6 DSP to execute custom algorithms. The company cited reduced development time and effort due to the ability to port its existing vision algorithms to run on the DSP, as well as the ability to achieve ISO 26262 ASIL D certification.

Toshiba also used Arteris IP’s Ncore Cache Coherent and FlexNoC non-coherent interconnect with the associated Resilience Package in the tapeout of its next generation automotive ADAS chip. The ADAS SoC includes image recognition and object detection using many processing engines and image processing accelerators, and Toshiba cited the IP’s flexibility as well as improved functional safety and overall diagnostic coverage.

Synopsys’ IP Business Unit achieved ISO 9001 Quality Management System certification by the British Standards Institute. The certification applies to all Synopsys worldwide development sites for DesignWare Logic Library, Embedded Memory, Interface, Processor, and Security IP products.

Numbers & People
AI inference processor company Mythic raised $30 million in Series B-1 funding led by Valor Equity Partners, with additional new investors Future Ventures, Atreides, Micron Ventures, and Lam Research.  Existing investors also participating included SoftBank Ventures Asia, Threshold Ventures (formerly DFJ Venture), Lux Capital, DCVC (Data Collective), AME Cloud Ventures, and Lockheed Martin Ventures, bringing total Series B funding to $70M.

UltraSoC named Barney Edgar the company’s new CFO. Edgar was Head of Finance at IoT company Arkessa, which was acquired by a private equity fund in 2018. Prior to Arkessa, he was Head of Finance at Neul, an IoT semiconductor start-up acquired by Huawei in 2014. “Issues like cybersecurity and functional safety are now everyday concerns for us all: UltraSoC has a huge opportunity to help address those,” said Edgar.

Events
ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.