Week In Review: Design, Low Power

VIP for Ethernet 800G; PCB design for students; EDA revenue up 2.2%.


Tools & IP
Synopsys debuted VIP and a UVM source code test suite for IP supporting Ethernet 800G. The VIP supports DesignWare 56G Ethernet, 112G Ethernet, and 112G USR/XSR PHYs for FinFET processes, which can be integrated for 800G implementations based on 8 lane x 100 Gb/s technology. The VIP can switch speed configurations dynamically at run time and includes a customizable set of frame generation and error injection capabilities. Source code UNH-IOL test suites are available for key Ethernet features and clauses.

Codasip released the latest versions of Codasip Studio and Codasip CodeSpace. Key features in 8.3 include minimal runtime library and minimal runtime, a memory interface arbiter, and tightly coupled memory.

CEVA’s CEVA-BX DSP cores and WhisPro speech recognition software targeting conversational AI and contextual awareness applications now support TensorFlow Lite for Microcontrollers, a cross-platform framework for deploying tiny machine learning on power-efficient processors in edge devices.

Mentor is providing students and instructors with a free 12-month license of its PADS Professional Design Suite (version 2.7) desktop software for design, validation, and manufacture of PCB-centric systems. The Student Edition includes resources including learning tutorials, how-to videos, and self-paced training.

Synopsys released the latest version of its LightTools illumination design software. Version 9.0 adds new tools to model and analyze polarizing elements with birefringent materials, used in applications such as AR/VR headsets and biomedical instruments, as well as new charts to assess the polarization state and orientation and identify how to maximize flux.

Achronix is using Synopsys’ DesignWare IP for PCIe 5.0 and DesignWare DDR4 IP for its latest family of high-performance Speedster7t FPGAs. Achronix noted the Controller IP for PCIe 5.0 implements a 512-bit datapath width supporting x16 links to deliver the maximum bandwidth required for the FPGA, while meeting low-power and low-latency requirements.

InterMotion Technology deployed Aldec’s Active-HDL for successful verification of its soft IP portfolio for the latest Lattice Semiconductor CrossLink FPGA. InterMotion cited the ability to create, simulate and debug soft IP designs in a shorter time with improved quality of verification and reliability of codes.

NETINT Technologies licensed Arteris IP’s FlexNoC Interconnect for use in its next-generation of enterprise SSD storage system controllers with on-chip video encoding processors. NETINT, which previously licensed the company’s interconnect IP in 2019, cited high bandwidth, low latency, data protection, and flexibility.

Rambus inked a patent license agreement with Utimaco, a supplier of Hardware Security Modules, that includes the use of Differential Power Analysis (DPA) Countermeasures for side-channel attack protection.

SiFive selected Synopsys’ Fusion Design Platform and Verification Continuum platform as part of its cloud-based methodology to create customized SoCs for customers.

EDA industry revenue increased 2.2% in Q4 2019 to $2626.3 million compared to the same quarter last year, according to the ESD Alliance. For 2019, the EDA industry revenue reached $10.2 billion which was an 8.3% increase over 2018. Strong growth in Europe, Middle East, and Africa pushed increasing revenues for the quarter, noted Walden C. Rhines, CEO Emeritus of Mentor. While most categories saw gains, the PCB and multi-chip module market stood out, with growth of 19.4% compared to Q4 2018 and a four-quarters moving average of 15.1%. The only category to fall was services, which saw a 15% decrease in revenue compared to Q4 2018 and 10.1% decline in the four-quarters moving average. Hiring remained up in tracked companies, with an 6.1% increase compared to a year ago and 1% from the previous quarter.

Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead? Plus, recent videos highlight well-understood approaches for safety-critical designs in Building A Safety Verification Flow and how HLS plus formal can significantly reduce optimization and debug time in Speeding Up Verification Using SystemC.

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