Whatever Happened To High-Level Synthesis?

A few years ago, (HLS) was probably the most talked about emerging technology. It was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area.

Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verification at Mentor, a Siemens Business; Dave Kelf, vice president of marketing for OneSpin Solutions; and Dave Pursley, product manager for HLS at Cadence. What follows are excerpts from the conversation.

SE: Ever since Mentor brought Calypto back in-house and Cadence acquired Forte, there has been little news about what is happening with High Level Synthesis. Why is that?

Bowyer: Information is driven by the tool vendors, and we have been busy over the past year. We have doubled the number of users, we have doubled the revenue, we broke into interesting new markets such as automotive and for controlling mirrors in 3D goggles, etc. A new technology gets less exciting when most people are ready to adopt it. Before then it is scary, and it has become less scary and thus less exciting. But that has led to more adoption of boring HLS.

Pursley: It is a good sign that it has become more boring. You don’t hear the discussions with customers and prospects. They are no longer asking if it really works, can you do this, is there a methodology that surrounds this? That is now accepted. You still have the question, ‘Will this work for me? How do I apply it to my design?’ The market is growing for us, as well. It’s a record year. We are seeing adoption in both new places and existing ones.

Kelf: Behavioral synthesis came out of Synopsys and that created a lot of excitement. Then they found out that people felt a disconnection between the behavioral side and RTL. It didn’t do very well and so things went quiet. Then HLS based on SystemC comes out, and there was a period of finding the application. Where does it fit and how does it get used? There was a lot of talk and discussion about that. Now there are key applications where it is paying off such, as in the graphics space. That means people are just getting their jobs done. It is a good sign, and the industry is maturing. Now the question is, ‘How does it expand and grow into areas that have more control logic, in automotive? How will HLS mature across the whole market rather that in small silos?’

SE: What has changed in terms of the types of designs or sizes of the designs that can be tackled?

Bowyer: The interesting thing is that smaller designs are being tackled. It used to be only the biggest, hairiest designs because you had no chance of designing it well in RTL. Now, as you get more experienced users, they are using it for designs that may only have 10,000 gates because they don’t want to go back to RTL. That has been the trend.

Kelf: Perhaps, because we are involved with formal, we do see a lot more control dominated designs as well these days. In the early days it was graphics and DSP – all very much datapath designs. Now we are seeing more control and people are moving from parts of the design to the entire thing.

Pursley: Absolutely. Adding control allows them to take the little pieces and also to put the sub-systems together including the bus interfaces, including the communications with the CPU or the controller or even an embedded fabric. This can now be handled automatically. We got this capability almost for free when we merged these two technologies.

Bowyer: That has led to a lot more interest on the verification side because as soon as you can do all of the stuff in one model, now you start asking about the ways in which this abstract model can be used. What can I do with it? The model executes faster than RTL but it does not simulate exactly the same, so how do I turn the fast simulation into a benefit and reduce the cost of RTL verification?

Kelf: The whole design flow is maturing. It is not just the synthesis part, but now includes the verification part. Commercial simulators now support SystemC, and it is not just the OSCI simulator being used anymore. You have all of the debugging power and now we have formal as well. It lets you do some of the code checking at a higher level that you may not be able to at RTL, which was one of the reasons for going to C++ in the first place. But there is no X state in C++, so instead you can use formal to figure out stuff about the unintialized state. This broadens out the use model and lets people use it in a more mature fashion.

Pursley: Yes, it allows you to approach SystemC-based hardware design as hardware design.

Bowyer: And we did get a synthesis subset last year. This is not just for synthesis, but formal can build upon that, as well. Formal almost needs synthesizable code in order to be able to function. Now you have a standard that allows everyone to come together and start to build tools around it.

SE: Has that standard had a significant impact or were the vendors already aligned?

Bowyer: Technically it did not have a great impact because we had to line up to write the standard. But perception-wise, there are a lot of customers who now feel more comfortable knowing that you can have a simulator and synthesis tool and a formal engine and a property checker and a linter. And there is a document that you can go to validate what the status should be.

Pursley: Yes, it is a tangible proof that these companies do actually work together, and there is an ecosystem, and that we are not just saying the words.

Kelf: We do still find that you have to work with customer to see what libraries they are using. They may include things that are not part of the standard, and we have to make sure it will work properly. There are still some deficiencies, such as you can write SystemVerilog assertions in with the SystemC code, and that is useful for consistency checking. But are we going to go from C asserts, where we now have an insertion standard that can allow a more comprehensive SystemC type of assertion on temporal things, more along the lines of SystemVerilog? That still has to come.

Bowyer: And interfaces. We need an interface library.

Kelf: Yes.

Bowyer: It is a standard for formal properties or assertions and a standard for interface libraries. Those have to be the next focus.

SE: How will the subset evolve over time?

Pursley: For the most part, the subset has focused on what we should be able to synthesize. It turns out that everyone can agree on that and for the most part there are some things on both edges that we had to add, but for the most part these are the things we should do. We focused on writing the right standard as opposed to trying to get each widget into the standard that would give us an advantage. In the end, that does not help. It is still evolving and we need to be aligned.

Kelf: Being involved in some other standards, SystemC is being put together by mature people who are trying to do the right thing for the users, as opposed to some other standards that will remain unmentioned. We all know the horror shows around competitive battles in those areas. It is not just the language subset, but the verification effort and other things surrounding it. They are all working on the right intent to produce something that is useable and the end users are comfortable with. You don’t see this that often in the standards committees. (See related story, Users Talk Back on Standards Process)

SE: There has been speculation and chatter about the end of and this may mean that design becomes a lot more important. If it is slowing down will that have a big impact on how many people turn to HLS?

Bowyer: You will see a lot more care go into architectural design. Does that lead to more HLS usage? I don’t know, but it does lead to more importance for selecting a good architecture because you don’t get a free lunch anymore. You cannot just go to the next node. So that will mean more redesign. It is new to us, as well.

Kelf: One way to look at is, if you cannot accelerate from node changes and get that benefit, then perhaps you have to speed up the design cycle. If you get more design done in the same amount of time, then you can get advantages there. That enables you to keep up with Moore’s law. That means using HLS and abstraction to get the pipelines carved out quicker and more efficiently. The time to market pressure is getting higher and HLS has a huge role to play.

Pursley: We have been doing a blog series entitled, ‘Making hardware design great again.’ It’s going to be huge. What it is really about is when we grew up and thought we were going to be hardware designers you expected to get some specs and review them, and then would look at some implementations, etc. But what happens in the real world? You created the previous version in RTL, and by the time that is done, you now need a slightly different version and you are just turning the crank. There is not a lot of design work. So, the quality of life improvement for the designer is to actually do some design—what they were trained to do—to figure out the architecture, the memory, the way that things will communicate from a macro level, is this hardware or software? They can do that work and still have time to meet their goals, and in the end they have a piece of IP that is more reusable, not just in subsequent technology nodes, but also if the algorithm needs to change or if the interfaces need to change. These become easy things to modify.

Kelf: The big question is where you spend your time? Is it down at the RTL or even gate level to make small changes? Or if you invest the same time at the architectural level, then that can have a more dramatic impact on the design so you end up with the improvements that you really need.

Bowyer: As companies stay with a process node, they are no longer driven by the next process node, and their design cycle becomes more decoupled. They can do whatever they want timewise. Most people will still target Christmas for consumer electronics, but you see many other industries where their design cycles were tied to the next process node. That is no longer the case. I would assume that means a faster design cycle.

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