Without Moore’s Law: EDA

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node.

In this article we examine the impact that a slowing in adoption rates would have on the EDA industry. This is not a new phenomenon. In fact, it has been happening for a few nodes already, where a smaller number of system companies, and lower number of design starts, have to pay for the increasing costs associated with the latest node. At some point, it would appear as if the back of the camel will break. Is that at 20nm, 14nm, 5nm?

“We still see a large number of users going off and designing at the 20nm/16nm/14nm nodes,” says Joseph Sawicki, vice president and general manager of the Design to Silicon Division of Mentor Graphics. “We are even having our first conversations about supporting 10nm tapeouts. The economics seem to be positive here for at least the next few years.”

He’s not alone in that assessment. “I don’t think that the semiconductor industry is going to shrink anytime soon,” says George Janac, chief executive officer at Chip Path Design Systems. “Semiconductors are going into everything. The application space will be covered by fewer chips even while the application space is expanding, such as developments in IoT or wearable computing. This sounds like a paradox, but the point is that applications will be differentiated by the software using the same chips.”

So where does EDA fit into this picture? Should it continue generating tools at the most advanced nodes? “The question to EDA vendors is not one of, ‘Should we?’” says Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy. “It is an imperative. Without EDA enablement and IP a new node cannot come to market. The question of, ‘Was it worth it?’ will depend upon the quality of the execution. The EDA companies that do the best job in bringing the value of a new process node to its greatest potential will be rewarded with market share gains.”

That appears to be the prevailing view. “The ecosystem enablement of advanced process technologies, physical IP and EDA, is necessary for the adoption of new process technology,” says Ron Moore, vice president of marketing for the Physical Design Group at ARM. “Fewer customers in the first-wave may change the development model to emphasize more collaboration between EDA, foundries, IP suppliers and their customers.”

The list of applications that will utilize those advanced nodes should come as no surprise to anyone in the semiconductor industry.

“What we have seen is that applications targeted towards high performance tend to move to the latest, most advanced geometries for the performance, power and area benefits,” explains Mary Ann White, product marketing director for the Galaxy Implementation Platform at Synopsys. “Although it is true that these types of companies may not make up the majority of actual design tapeouts, their products tend to be extremely high volume. They definitely share the cost burden of ‘risk’ production on more advanced process nodes, but their end-market is always hungry for more functionality, faster, so plans to move to the smaller transistors seem to be a permanent plan.”

What has changed significantly, though, is the price/performance equation. “We have already seen the substantial price increases in advanced CPUs, reflecting a similar/related trend,” points out Drew Wingard chief technology officer of Sonics. “Large semiconductor companies have traditionally capped their total EDA spend as a percentage of the semiconductor revenue. With this model, it is difficult to see how the bleeding edge designs will be able to pay enough to cover both the ever-increasing EDA development costs and the lost EDA revenue from folks who wait for process maturity.”

Business Models Changing
Is there a way in which the business model for EDA companies can change to ensure their continued investment?

“Designing at new nodes will be challenging and expensive,” notes Bruce McGaughy, chief technology officer and senior vice president of engineering of ProPlus Design Solutions. “EDA vendors should be given incentives to develop necessary tools. In the meantime, better collaboration between EDA vendors and foundries is needed to tackle those new challenges.”

At the most advanced geometries, that is one of the big changes.

“14nm and below require an extremely close cooperation between foundry and EDA company,” says Marco Brambilla, director of engineering for Synapse Design. “This means that the total cost goes up, and ownership of the end result becomes muddier. I don’t think ST would want Synopsys to explain to TSMC how they solved a certain problem.”

And given that economics was the basis of Moore’s Law, these shifts have evoked some very strong opinions.

“Going forward there will need to be a new business model,” says Hem Hingarh, vice president of engineering at Synapse Design. “An example could be some kind of royalty between EDA companies and product companies.”

Adds Bob Smith, senior vice president of marketing and business development at Uniquify: “We might see larger companies invest to develop their own solutions in a throwback to the past.”

Many look at the investments EDA companies are making to diversify their revenue stream, such as IP, application software tools and into vertical markets such as automotive.

Sonics’ Wingard paints a somewhat bleak picture for the future. “I believe that the all-you-can-eat deals spread over multiple years means that there isn’t any real financial upside for an EDA company to improve their products except for displacing revenue from a competitor. My prediction is that EDA companies will be driven to become even more competitive in the short term. In the medium term, some companies will likely be forced to drop some of their solutions, thus eliminating customer choice. Only then, in a reduced competition market, can prices actually rise. Of course, this situation is bad for everyone involved!”

Additional Effort on Existing Nodes
Adoption of the latest node is not the only way to improve designs, and there are many EDA companies that get revenue from things other than the back end process.

“To put the next-node debate in perspective, we should remind ourselves that Moore’s Law and semiconductor innovation are not the same thing,” explains Sawicki. “That is, transistor size scaling is just one dimension of innovation. There is a lot of innovation occurring at established nodes, and this is driving the adoption of advanced EDA solutions.”

“More than the tools, designers want to improve their designs for the maximum cost advantage and differentiation,” says Anand Iyer, director of product marketing at Calypto. “While migrating to a new node helps, they also look at tools for achieving this purpose.”

Aveek Sarkar, vice president of product engineering and support at Ansys-Apache, points out that “the work that is being done to achieve the accuracy and capacity requirements for 14/16nm technologies are immediately benefitting design teams who continue to use 28nm or are moving to 28nm.”

Charlie Cheng, chief executive officer of Kilopass Technology believes there are several developments that can be made at 28nm to fill the hole created by breaking Moore’s Law. Examples he provides include tools for changing bus widths so that throughput can be increased, a new SRAM that is smaller and low power and a new transistor formation in 28nm that can enable much higher switching speed and drive current to enable next generation SerDes.

In part two of this article, more of the ideas that companies have for breathing additional life, and hopefully revenue, into the 28nm node will be examined.

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