What’s needed for RTL testability and analysis and why RTL analysis is so important for DFT.
The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimization for fast simulation or even the ability to synthesize or meet testability goals.
The test coverage goals for advanced deep submicron designs are in the order of 99.5% for stuck-at faults and over 90% for transition faults. These high coverage goals can only be achieved by analyzing for testability and making design changes at RTL. To read more, click here.