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Parallel RTL Exploration With Unparalleled Accuracy


Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

Side-Channel Attacks Make Devices Vulnerable


As the world begins to take security more seriously, it becomes evident that a device is only as secure as its weakest component. No device can be made secure by protecting against a single kind of attack. Hypervisors add a layer of separation between tasks making sure that one task cannot steal secrets from another. Protection of the JTAG port is necessary to prevent access underneath the h... » read more

Is it Hot? Ask Joules


Over the last decade it has become clear that power reduction techniques involving different parts of the chips would become more important than they had historically. In 2G cell phones everything except the real-time clock could be turned off when the phone was not in use. Pre-smartphones, a phone was either making a call (or texting, gaming, etc.) or it was off. In fact, a cell phone can’t ... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL


The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL


The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more