Future of EDA; power management trends; SFMTA hit by ransomware; automotive security.
Cadence’s Paul McLellan presents a three-part series on the future of EDA, with insights from both academia and industry.
Mentor’s Harry Foster focuses on power management trends in ASIC design, in the latest installment of the 2016 Wilson Research Group verification study. Plus, what aspects of power are verified and how designers describe power intent.
Synopsys’ Robert Vamosi reports that the San Francisco Municipal Railway System suffered a massive ransomware attack on Friday with ticket vending screens citywide displaying the message “You Hacked, ALL Data Encrypted.”
Rambus’ Aharon Etengoff listens in on a talk by Joe Gullo on why a multi-faceted design approach is required for automotive security.
The White House’s Megan Smith and Laura Weidman Powers look at what works in building a more diverse workforce for science and technology companies.
NXP’s Michele Pio di Monte argues that RFID could have big benefits for smart manufacturing and Industry 4.0.
In a video, a Lam Research staff writer gives a brief overview of litho-etch litho-etch and self-aligned multipatterning techniques.
ARM’s Freddi Jeffries checks out the basics of building 360 degree video.
GlobalFoundries’ Jim Rogers takes a look at the company’s 14nm finFET process technology and the approach used to produce a new networking chip.
Mentor’s Craig Armenti says that PCB design is undergoing a big shift.
And don’t forget the blogs featured in last week’s System-Level Design newsletter:
Editor In Chief Ed Sperling contends that consolidation is raising the threat level from some well-financed but unfamiliar players.
Technology Editor Brian Bailey looks back on what were the most popular stories this year.
OneSpin’s Dave Kelf questions whether specialist teams limit the realization of a technology’s full potential.
Mentor Graphics’ Dave Wiens argues that as designs get more complex, design teams need an environment that supports collaboration.
Cadence’s Frank Schirrmeister compares feedback loops to assessing costs and applies both to ticket sales and verification.
Aldec’s Zibi Zalewski explains how to use FPGAs to optimize high-performance computing, without specialized knowledge.
ARM’s Darren Cepulis observes that alternative HPC architectures will only happen if a strong supporting software ecosystem is in place.