category: Technical Papers

category: IoT, Security & Automotive

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich et al.)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A technical paper titled "Data-driven power modeling and monitoring via hardware performance counter tracking" was published by researchers at ETH Zürich, Scuola Superiore Sant’Anna, RISE Research Institutes of Sweden and University of Bologna. Abstract "Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an afforda... » read more

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms" was published by Georgia Tech. Abstract "In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth... » read more

High-Performance p-type 2D FETs By Nitric Oxide Doping (Penn State)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "High-performance p-type bilayer WSe2 field effect transistors by nitric oxide doping" was published by researchers at Penn State University and Florida International University. Abstract "Two-dimensional (2D) materials are promising candidates for next-generation electronics, but the realization of high-performance p-type 2D field-effect transistors (FETs) has... » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)
By Technical Paper Link - 28 Jun, 2025 - Comments: 0

A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Viability of aZnMIm As A Resist For EUV Lithography (Johns Hopkins, Northwestern, Intel et al.)
By Technical Paper Link - 27 Jun, 2025 - Comments: 0

A new technical paper (preprint) titled "Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous Zeolitic Imidazolate Resists Deposited by Atomic/Molecular Layer Deposition" was published by researchers at Johns Hopkins University, Northwestern University, Intel Corporation, Bruker Nano, EUV Tech and Lawrence Berkeley National Lab. The paper states "This study demonstr... » read more

GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores
By Technical Paper Link - 26 Jun, 2025 - Comments: 0

A new technical paper titled "TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs" was published by researchers at University of Connecticut and University of Minnesota. Abstract "hip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being utilized. The use of th... » read more

HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)
By Technical Paper Link - 25 Jun, 2025 - Comments: 0

A new technical paper titled "SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models" was published by researchers at University of Florida. Abstract "Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, c... » read more

Device Architecture For 2D Material-Based mNS-FETs In Sub-1nm Nodes (Sungkyunkwan Univ., Alsemy)
By Technical Paper Link - 24 Jun, 2025 - Comments: 0

A new technical paper titled "Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes" was published by researchers at Sungkyunkwan University and Alsemy Inc. "This paper explores the design and optimization of multi-Nanosheet Field-Effect Transistors (mNS-FETs) employing a Transition Metal Dichalcogenide (TMDC) channel, specifically MoS2, for the 0.7 nm technology node u... » read more

Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 
By Technical Paper Link - 24 Jun, 2025 - Comments: 0

A new technical paper titled "Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration" was published by researchers at Yokohama National University, TEL, SK hynix, and University of Tsukuba. According to the paper: "Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface... » read more

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