Do SoCs Need Earthquake Insurance?

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Increasing IP integration and advanced node complexity is putting more focus on RTL design data to improve sign-off and predictability.

RTL sign-off is not a new term, but with SoCs that can be comprised of up to 90% IP blocks combined with the complexities that advanced manufacturing process nodes bring, RTL sign-off activities become a process that demands a more comprehensive approach.

“There is a fundamental shift going on in chip design in general in that there is a bigger focus on so-called system on chip (SoC) design. That’s a term that’s used quite liberally but really if you get down to it what you are doing is integrating a whole bunch of functions that in the past would be a complete board or a system now has turned into the chip. What you are doing is integrating a lot of different functions which manifest themselves as IP blocks whether they are developed internally by a big semiconductor or chip company or sourced from commercial vendors like an ARM or a Synopsys,” according to Piyush Sancheti, vice president of marketing at Atrenta.

This reliance on IP creates a fundamental shift in the way people do design, Sancheti said. Most blocks come to the engineering team as soft IP or as an RTL. “Most big IP companies don’t really sell RTL, they sell an RTL configurator so the design team goes on a portal, configures their IP and then get the RTL. As a result if I’m doing an SoC design there is a lot of content that is coming to me through third parties or a lot of content that I am re-using from the previous generation of the design. The common thread is that it starts at RTL and now I put all this together and I have to make sure that it all works together not just functionally but in terms of area, timing, power, testability requirements, and I have to make sure that all of my blocks are clean, that all of them play nicely before I commit to implementation, before I get into synthesis, place and route.”

Along these lines, Anand Iyer, director of product marketing at Calypto, noted there are still many challenges that the EDA industry is trying to address, including how to accurately estimate performance and power at RTL given process variation and special recipes used for timing closure at the backend, which becomes even more apparent when designing an IP that needs to work in several usage modes.

However, Gal Hasson, senior director of marketing, for RTL Synthesis and Test at Synopsys said that while he does think there is increased activity in this area he would not necessarily categorize it as RTL sign-off. “The one place where people will want to do more of that activity … is where customers hand off RTL to a third party to implement a design for them. Some of the ASIC vendors are doing a little bit of that. This is still very small in terms of the volume but there is a little bit of it. What we do see a lot is very big emphasis on the RTL in two aspects. One is being able to generate high-quality design data – the RTL with the constraints, the power intent – so I would use a broader term. We call it design data.”

There is really a big push within the customer base to be able to come up with this entry data for the implementation, which is of high quality. In this context, he explained, high-quality means knowing with a fairly high degree of confidence that they take this design, RTL constraints, power intent, into the implementation and go through synthesis, place and route, that it will actually get them where they need to get in terms of the timing, the performance of the chip, the area of the chip, the power consumption of the chip. Essentially, that it meets their goals.

Design teams also want to make sure that the flow is going to be convergent, Hasson continued. “That’s another metric that they will look at when they think about whether this is this high-quality RTL and design data. By convergent I mean you can have the greatest prediction that this RTL, once you take it through the implementation, you will get a chip that operates at whatever frequency you want it to operate at. But then you find out, when you go to place and route, that there’s too much congestion and it cannot be routed. Then the whole thing goes out the door and you have to go back and reconsider what to do in the RTL, and that can be extremely costly so quality from that perspective.”

Those are some of the key considerations driving designers to look at RTL exploration capabilities and tools so they can shorten their design cycles and make sure early on they get the quality of design that they need, he said.

“My view is that this will evolve in a slightly different direction than ‘sign-off.’ How common is it that a customer will be able to sign-off on the RTL and actually go implement it and the RTL doesn’t change? Today with the dynamic markets, requests keep coming in, spec changes — I’m hearing from customers that they are changing their RTL until the very last minute — until the end implementation. What they really are asking for in those cases are the capabilities that will allow them to very quickly assess if the change that they need to make is going to have significant negative impacts on this design.”

How power fits into RTL sign-off
Power is a challenge in recent years because today’s design starts are driven by a thermal design power (TDP) constraint, Iyer noted. TDP is defined as the maximum power for a chip before it goes to thermal runaway; 80% of power dissipation of a chip is decided at RTL. Because of this, designers want to predict the final chip power at RTL but accurate RTL power analysis requires advanced tools. “First, we need to bring physical awareness to the RTL power analysis. This means modeling the clock tree, taking into account multiple Vth offered by the process technology and using SPEF to scale the wire capacitances. Second, we need accurate switching activities at all nodes through sequential analysis. With such analysis, designers will be able to sign-off on power at RTL across multiple usage modes.”

When considering power in the context of RTL sign-off, Hasson said, “You have some thoughts about what you need from this design in terms of the power consumption. How do you actually come up with the right assessment of power intent, the power architecture? How many power domains are you going to have? What is going to be on and off when? Is that going to give you what you need?”

Tools for early design exploration today can take a very minimal subset of the UPF power intent and tell you the legal states of the design, he said. “What power saving can I expect if I turn this and this block off for power domains off what the power architecture is going to look like. A key capability that has to be there for all of those tools that claim to provide information, analyze, assess or sign-off the RTL has to be very tightly correlated to the implementation.”

Yoon Kim, group director, front end design marketing at Cadence agreed. “Everybody is using multiple IPs and advanced node processes — combining those two we are at an inflection point where people are really nervous about total turnaround time and predictability. How am I going to know, once I start my design, how long is it going to take? What if I miss something? Do I have to go through the whole iteration over and over again? Customers did that all along, but up to a certain point they thought it was expected, that iterations happen. I go back all the way through the design process, I go back to my RTL and do this big loop over and over again. But at the advanced nodes, you can’t really do that. It just takes way too much time. So they are looking for a way to cut down the turnaround time. On top of that, it’s not just the turnaround time. It is about the want some sort of accuracy. We need to make sure the quality of the result is there. It’s not just to simply follow a checklist and then I’m done. How do I know that whatever I completed in the front end space is actually what I’m going to see the back end? The entire RTL sign-off must be tied to the implementation production tool – synthesis, place and route, and sign-off.”

What people are doing today
Sancheti observed that in the past people would do is synthesis first. “As soon as an RTL was simulating and every thing was toggling right, people would synthesize it right away and to then start polishing it and doing the feasibility of it. What we see happening in the industry is people want to do synthesis last. If you can do a lot of the feasibility up front and of the design flow make sure that RTL is ready for implementation it makes life that much easier for you in the back end.”

For this reason, he said RTL sign-off should be comprehensive to try to prevent nasty surprises coming to you at the back end of the design flow. “We pretty much create a prototype of the design. We are mimicking what your implementation tools are going to do downstream, but we are doing it in a way that it is fast, efficient, and there are still links back to the RTL. You want to have as many aspects of your design covered in the sign-off phase, but if you don’t it’s not the end of the world because you are going to detect or uncover them later in the design flow hopefully. Worst-case scenario: You find it in silicon or in the actual device once it is in the field where deployed. From that standpoint, if you are trying to minimize your design risk you obviously want to do as many things as possible at the front end of the design flow. That is why we constantly emphasize that if you are buying an insurance policy you want that insurance policy to cover as many calamities as possible. We have customers that say, ‘I like XYZ for that,’ and we say that’s fine as long as you have a proper methodology just like if you live in California, you can live without earthquake insurance but I think it makes good financial sense.”

Arvind Shanmugavel, senior director, applications engineering at Apache Design, added that traditional sign-off for IC design has mostly revolved around timing, functionality and physical design verification. “RTL sign-off is a new paradigm shift in the past few years due to the heavy focus on low power methodologies. Checks for power intent verification, clock domain crossing and lint checks are quite common in RTL sign-off flows nowadays. However, designers are now going one step further, including analysis driven power metrics for RTL sign-off.”

He suggested the following analysis driven power metrics at the RTL stage:

  • Clock gating efficiency: This metric shows the percentage of time that gated clocks are turned off for a particular vector. This report is per clock gating instance (either inferred or instantiated).
  • Clock gating enable efficiency: This metric shows the percentage of time data has changed wrt the time clock is enabled (which is based on enable duty). The ideal case would be to have 100% clock gating enable efficiency.
  • Clock vs data activity checks: This check shows the average activity of the clock and data elements in a logical hierarchy. This is an indirect representation of power efficiency for a block.
  • Un-gated registers: This check simply reports the list of un-gated registers in a design or logical hierarchy. It captures free running clocks to registers.
  • Power density: This check provides a metric of power per unit area based on the number of inferenced gate elements. This check ensures that blocks do not have a disproportionate amount of power density from the average power density of the chip.
  • Activity annotation: This check provides annotation statistics for each vector used during power analysis. Helps ensure that power analysis is properly done at the RTL stage.
  • Vector coverage: Ensures that a proper set of vectors are chosen for all RTL power analysis. Typically, worst case power, idle and reset vectors are chosen. Users can generate a single power report based on multiple such vectors as well.

Bottom line: While it is agreed that IP and advanced nodes are causing more focus to be placed on an RTL sign-off methodology, the right path to get there depends on whom you ask.




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  • http://www.realintent.com/ Graham Bell

    Design sign-off certainly needs to be comprehensive at the RTL stage. Standing behind functional verification sign-off are three technologies: structural, formal and dynamic analysis.
    Today we see the static verification category being used to cover both structural and formal methods. The promise of Static verification is that it can replace simulation (a dynamic
    method). For each of the potential problem areas of a design (clock-domain crossing, power, etc.), specific solutions can be created that use the right mix of these methods.
    There are different kinds of functional verification that employ these static methods. Automatic formal verification uncovers hidden bugs that were not visible to the designer. Deadlock between two interlocking FSMs for an example, or all arcs will transition correctly.
    A rising area of concern is X-propagation verification. RTL simulation be its very nature is X-optimistic and can hide bugs. Designers need to understand what are the most X-sensitive constructs in their design and how they can be affected by upstream X-source.s. Another key area of concern is ensuring that designs come out of power-up in a known state in a given number of clock cycles. Static analysis methods are the only means to ensure this in a reasonable amount. Simulation takes too long to do this.
    Sequential equivalency checking is another area that is very important. It proves that the various power optimizations done by design teams has not broken the functionality of the design. These kind of optimizations also affect the interfaces between different IP blocks and CDC verification must be done after these design changes to ensure correct clock synchronization is occurring.
    The comprehensive approach to RTL verification is being adopted by many companies. However, semiconductor technology leaders are looking to a best-in-class approach for the sign-off tools. While a single vendor may offer a breadth of offerings, it remains an open question if each sign-off category is delivering best-in-class performance. Indeed semiconductor companies will adopt a mix of technologies from companies such as Real Intent, Calypto, Defacto and Excellicon because they deliver the leading edge performance capacity and design management they are looking.
    The drumbeat of growing complexity is requiring retooling of tools technologies. RTL linting has been a verification tool is use for other 20 years. However only the most-recently developed tools are deliver gigagate capacity. Designers need to have answers in minutes and be able to quickly resolve any issues. Best-in-class besides cover speed and capacity must also provide smart low-noise reporting. This means highlighting the most important debug issues that will have the greatest impact in removing issues from the design. A hierarchical organization, and carefully engineered rulesets keeps designers productive.
    And one more thing to cover is the issue of data models that are used to represesnt the analysis a design at the IP or block level. When doing full-chip SoC integration the details of the IP blocks must be retained intelligently to ensure that “sneak paths” that may be lurking in the IP and only come into play at the SoC level can be uncovered. Abstraction models are infamous for ignoring that essential detail that may needed for top-level analysis.
    To summarize design managers understand the comprehensive list they need to sign-off for their designs. To have it imposed as a standard by a single vendor, certainly makes that vendor happy but may restrict the freedom of design managers to do what they think best.

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