While design costs have been rising steadily since 40nm, the acceleration at 7nm and 5nm is worrisome.
If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design costs), the overall impact can be similar. In this case, the number of design starts is impacted by the climate of rising design costs.
Following are a few of Semico’s findings.
As SoC design costs increase at each succeeding process node there could be several impacts to the market.
Many of these statements are not new to most people. Design costs have been rising steadily since the 40nm node, but it is the acceleration in design costs at 7nm and 5nm that are the most worrisome to the industry. Mobile and Wireless, Artificial Intelligence, Deep Learning / Big Data, ADAS and Embedded Vision will require high complexity silicon and will utilize the advanced nodes. Semico believes these applications will push the market leaders to utilize the ‘bleeding edge’ process technology.
But Semico is already observing a shift in the companies that participate in the second wave of designs. One of the major sources of innovation is found in the designs accomplished by the second wave of products that are introduced by companies that trail the bleeding edge. The functionality and rich feature sets that are found in advanced designs have provided a path for pioneering but less complex designs two or three years later. Once these designs have been proven and the cost structure to create them has become more moderated, other designers jump on the bandwagon. This has always been the case in the semiconductor industry and is not a new trend. However, Semico has observed a lengthening of the time interval between the initial entrants and when the 2nd wave companies are able to deliver their solutions.
Semico is forecasting that the Compound Annual Growth Rate (CAGR) for designs of Advanced Performance Multicore SoCs will be in the 3.2% range over the next 5 years. These are the design starts that will mostly be aimed at the new applications entering the market.
While the far future is somewhat cloudy, the near term still shows reasonable growth for the nodes down to 10nm. Beyond 10nm, design starts are going to be more constrained by rising design costs. Although Semico does not see the total number of designs that migrate to the new nodes being appreciably different than in previous process geometry transitions, we do believe the time frame for such transitions by the majority of companies doing designs at these levels will be somewhat longer.
These findings will be detailed in two new reports on the ASIC Design Landscape; SC105-17 and SC106-17. Semico would like to hear your opinion on this very important issue.
Do you think that the accelerated increase in design costs associated with 7nm and 5nm designs, will lengthen the time interval between the initial users of these geometries and the 2nd wave of product designs?