LP Test

By Luke Lang
Last month, we discussed testing a portion of a chip at a time to reduce overall power dissipation during test. However, this does not address local power dissipation hotspots that can cause excessive IR drop. These hotspots can occur in regions where many nets are switching at the same time.

Typically, a chip’s power grid is designed to meet IR drop specification in the functional mode, where the average toggle rate is about 10% to 15%. In test mode, the average toggle rate of ATPG patterns can be higher than 40%. Depending on the clock frequency, this dramatic increase in toggle rate could mean significant increase in IR drop. If this is not analyzed, excessive IR drop will degrade the propagation delay of logic gates and cause timing violations. This means that a perfectly good chip could fail ATPG test.

This kind of failure is often difficult to pinpoint. Typically, it is reflected in poor yield. A test engineer will probably run the test again at a reduced clock frequency. If the yield goes up, then it is very likely that we have excessive IR drop. But this may not be how we want to fix the problem. Test time is very expensive.

Another way to accommodate IR drop in test mode is to beef up the power grid. This could represent significant increase in die size and cost. It is difficult to justify such an expense for a one-time event.

Fortunately, there is another method to deal with this issue. We could ask the ATPG tool to limit the toggle rate of the test pattern. A pattern with alternating 0 and 1 will probably give the highest toggle rate. A pattern with constant 0 or 1 will have zero toggle rate. Looking at these two extremes, it is clear that higher toggle rate will produce better test coverage. To control power, we must lower toggle rate, which will most likely have a negative impact on test coverage. To recover the lost coverage, we need additional test patterns and test time. Therefore, we need to carefully balance toggle rate, test coverage, and test time. This can be done by analyzing the IR drop characteristics of each pattern. We want to reduce toggle rate just enough to eliminate all IR drop hotspots.

Fortunately, toggle rate vs. test coverage is not that significant of a problem. If we plot test coverage against the number of test patterns, we will see that test coverage ramps up very quickly with the first few patterns. Subsequent patterns test the difficult faults. Many bits in these patterns are ‘don’t care’ bits. When we reduce the toggle rate of the initial patterns, the lost coverage can be picked up by the ‘don’t care’ bits of the subsequent patterns. What we end up with is a plot that does not ramp up as fast but still achieves reasonable test coverage. If additional test patterns are needed, it is usually not that excessive.

I once spoke to an engineer who was having this exact IR drop problem. He was generating new ATPG patterns with controlled toggle rate and verifying the reduction of IR drop by analyzing yield. He was manually turning the toggle rate knob until he reached acceptable yield. This is certainly a workable solution, but I’m not sure if it is the most efficient solution. Given that he already has silicon in hand, perhaps it is. But I have always wondered if he could have reached the end goal quicker by analyzing the IR drop of the various ATPG patterns with a software tool first. This will take time, but it will also eliminate the need to analyze yield on the tester.

Power during test is a very real issue. It needs to be analyzed before tapeout. The software tools needed to address this issue is available. We just need to make sure that they are part of our design flow.

—Luke Lang is engineering director at Cadence Design Systems.