Manufacturing Bits: April 12

Ink FETs; vertical transistors, monolithic 3D.


Ink FETs
The University of Pennsylvania has developed a new way to make chips by using nanocrystal inks. The devices, dubbed nanocrystal field-effect transistors (FETs), could be used one day to develop chips for flexible and wearable applications

In the lab, researchers devised spherical nanoscale particles. These particles, which have electrical characteristics, were dispersed in a liquid. The resulting materials were called nanocrystal inks.

Four types of inks were then developed, including a conductor (silver), an insulator (aluminum oxide), a semiconductor (cadmium selenide) and a conductor combined with a dopant (a mixture of silver and indium), according to researchers at the University of Pennsylvania.

Then, the inks were used to make nanocrystal FETs. In the flow, a mask is formed. Then, a conductive silver nanocrystal ink was deposited from liquid on a flexible plastic surface.

The mask is removed. As a result, the silver ink forms a gate electrode. Then, a layer of an aluminum oxide nanocrystal-based insulator is spin coated on the surface.

Following that, a layer of cadmium selenide nanocrystal-based semiconductor is deposited on top of that. Finally, an indium/silver mixture forms the source and drain.

Penn developed four nanocrystal inks that comprise the transistor, then deposited them on a flexible backing. (Source: University of Pennsylvania)

Penn developed four nanocrystal inks that comprise the transistor, then deposited them on a flexible backing. (Source: University of Pennsylvania)

When heated, the indium dopant is diffused into the device. “These materials are colloids just like the ink in your inkjet printer,” said Cherie Kagan, a professor at the University of Pennsylvania, “but you can get all the characteristics that you want and expect from the analogous bulk materials, such as whether they’re conductors, semiconductors or insulators.

“Making transistors over larger areas and at lower temperatures have been goals for an emerging class of technologies, when people think of the Internet of things, large area flexible electronics and wearable devices,” Kagan said on the university’s Web site. “We haven’t developed all of the necessary aspects so they could be printed yet, but because these materials are all solution-based, it demonstrates the promise of this materials class and sets the stage for additive manufacturing.”

Vertical transistors
Several years ago, a group from Carnegie Mellon University proposed a next-generation, vertical-like transistor type. The technology, dubbed Vertical Slit Transistor Based Integrated Circuits (VeSTICs), has recently resurfaced as a possible next-generation transistor candidate.

VeSTICs make use of a key element, dubbed a Vertical Slit Field Effect Transistor (VeSFET). In simple terms, a VeSFET is a junction-less device, in which the gate oxide is in a vertical plane. There are two gates per transistor.

The dual-gate transistor is surrounded by four metal pillars. They serve as gate terminals. There is also a source and drain on the device. A channel, or slit, between the two gates allow the current to flow.

VeSFETs can be arranged into an array of transistors, which are called VeSTIC Canvases. Test structures have been develop on silicon-on-insulator (SOI) substrates. “Comparisons of benchmark circuits implemented in standard cell style indicate that when operating at maximum speed, the power delay product of VeSFET designs is only 35% of the CMOS designs,” according to a paper from Wojciech Maly, a professor from the Electrical and Computer Engineering Department at Carnegie Mellon. “When running at the same speed, VeSFET designs consume only 35% dynamic power and 2.6% leakage power of the CMOS-based implementations.”

Monolithic 3D
Leti, an institute of CEA Tech, has announced the continuation of its collaboration with Qualcomm to develop Leti’s monolithic 3D technology.

The technology, dubbed CoolCube, is a sequential integration scheme that eliminates the need for through-silicon vias (TSVs) and enables the stacking of active layers of transistors in the third dimension.

As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs that will accelerate adoption of the technology. The extended project’s goals include building a complete CoolCube ecosystem that takes the technology from design to fabrication.

Leti CEO Marie Semeria said: “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”