Secure it early at RTL!
The recent 6.0 earthquake near Napa California caused close to $50 million in damages to the wineries and property in the region. The San Francisco bay area is accustomed to earthquakes and hence structural engineers design buildings to bear high intensity earthquakes amongst other natural disasters. The damage to property would have been much higher if not due to the strict guidelines followed during the construction of new buildings and their foundations, to increase robustness of the structures.
A similar analogy can easily be applied to semiconductor designs. Chip designers follow certain best practices to avoid last minute surprises, design re-spins and finding defective parts. If these best practices and design guidelines are not followed, it could very well result in a total disaster with soaring manufacturing costs and missed time to market windows in today’s competitive consumer markets.
As far as manufacturing test is concerned, this point in time is far too late to realize that the test patterns generated from the Automatic Test Pattern Generation (ATPG) tool does not meet the test quality requirements, which is typically ~99% for stuck-at test and over 80% for transition defects.
The main issue seen with manufacturing test vectors is the time spent to debug faulty patterns from actual silicon defects. As seen in Figure 1, test engineers would eventually realize that the pattern failures are due to glitches caused by the design structure and give feedback to the RTL designers to make changes, which causes a significant schedule delay in the tape out of the design.
An automotive chip manufacturer recently encountered a re-convergent asynchronous reset signal (Figure 2a), which caused pattern failures on the Automatic Test Equipment (ATE). The test engineers spent considerable time on the tester to determine if the failures were a result of bad input vectors or actual silicon defects. These test patterns could’ve been masked on the tester to cause the silicon to pass the test, resulting in the shipment of low quality parts. Is all this really worth it, especially if the chip is meant to control the air bag in your car?
RTL designers could easily fix issues with respect to re-convergent clocks or resets and sign off their design with high confidence to meet the test quality requirements by using a solution that provides analysis at RTL to catch issues, which could result in non-robust test patterns in ATPG (such as Atrenta’s SpyGlass DFT tool suite). An audit coverage report can also help designers to address the steps required to achieve the highest test quality at RTL. The test robustness section in such an audit report (Figure 2b) provides the information about the different rules that could impact the percentage of flip-flops in the design.
If you are concerned about the actions taken by this automotive chip manufacturer, fear not. They delayed their project schedule by three months to fix the re-convergent reset issue and have adopted RTL testability analysis for their next project!