Menta Embeds FPGA Programmability

What could be worse than developing the infrastructure that goes along with processor IP? Perhaps the tool chain required for an embedded FPGA.


What constitutes a startup can be a matter of the market segment you are going after and the type of product that you are building. Within EDA, we often think of the lifetime of a company being just a few years between when an opportunity is identified, to a product being built and getting the first few customers and then getting gobbled up by one of the big three. But when hardware is involved, things can take quite a lot longer. Even when that hardware is “soft” in the form of IP, there can be a lot of infrastructure that has to be put in place. One such startup is Menta, a French company started in 2003 that is now creating embeddable FPGA structures.

The notion of an embedded FPGA probably stayed under the radar for most people until Intel Corp. announced its acquisition of Altera. Suddenly, the industry started looking at the possibilities for combining a CPU with an FPGA and the applicability of that combination to a range of markets opportunities. Menta takes that a step further by eliminating the overhead of having two chips and adds additional flexibility by being able to custom match an FPGA core to a client’s specification.

Semiconductor Engineering talked with Yoan Dupret, business development manager for Menta.

SE: How would you categorize your solution?

Dupret: The programmable market can be divided in two ways. First, there is classic programmability that is used for time-based processing, and then there are processors used for parallel processing. An orthogonal way to categorize the solutions is based on being standalone-chips or IP solutions. Menta plays in the parallel programmable, IP space and has an embedded FPGA solution.

SE: What types of applications do you target?

Dupret: We believe that we can solve five types of problems. Often, designs have to start before they have the full specification. They need a solution where they can have some part of the logic be defined right at the end of the development. Another application is where a chip may have several sets of customer requirements in a small part of the chip and you had to create multiple variants. An example is with cryptographic blocks where there are different requirements for different countries or for local regulations. A third application is where you are fighting obsolescence of the chip. This often happens in inkjet cartridges for printers. The fourth application is for designs that require tuning where you may want to be able to do that in a programmable solution. An example is a FIR filter as found in radio chips. The fifth application, which is where Intel/Altera integration fits, is to create a CPU co-processor.

SE: Cryptography is attracting a lot of attention today. How can the problem be attacked different with an eFPGA solution?

Dupret: An eFPGA not only adds flexibility with the programmability of the solution, but also adds additional security because there is nothing going out of the chip. You can also regularly change the algorithms in a random way. Plus, to break it, you now need to know both the bitstream content and the architecture of the eFPGA before you would be able to decode anything. This makes reverse engineering very difficult.

SE: What makes your solution highly configurable?

Dupret: Our solution has lots of flexibility built into the architecture. Just like any FPGA, we have embedded logic blocks implemented as Look Up Tables (LUTs). Our blocks have integrated carry chain inside the blocks. We also have programmable I/O that enables the FPGA resource to be connected to the other parts of the chip. The architecture can be embedded into a classical ASIC flow. One important aspect of this is that we are not SRAM-based and use only standard cells. Plus, we integrate into a classic Scan Test methodology. There are two other types of blocks we offer. The first are embedded memory blocks, which utilize any memory cell from the foundries. Alternatively, they can use memory outside of the FPGA, but embedding it provides faster access. Finally, customer blocks, which are hard IP provided by the customer, can be integrated. A common example of this would be a DSP block or a MAC.

SE: How are those resources put together?

Dupret: For customers wanting to get started quickly, we provide some pre-configured blocks. This lowers the delivery time and these are shipped as hard IP. Then the customer just has to deal with the programming of the device which is handled through our tool flow (Origami Programmer). But we can also do custom eFPGAs that are tailored to the customer needs and can be optimized for their speed and power requirements. To help with the specification, we have software (Origami Designer) that helps with the design.

SE: It would seem that the software problem is probably larger than the hardware one. How many of the engineers are working on hardware and how many of software?

Dupret: Menta started out as a software company and a lot of the innovation comes from the software folks. We also have a few experienced hardware engineers. The split is about half and half.

SE: There are an increasing number of fabrication technologies and nodes these days. Does this create a support nightmare?

Dupret: It is a challenge to support all of the foundries and all of their processes. This creates more work and the newer technologies have greater demands on us.

Menta does have some competition in the eFPGA space, from companies with roots in France. One of them was created by the original founders of Meta Systems, a French company that Mentor Graphics bought for their emulation technology back in 1996. Another competitor was formed by people who continued to work on that technology within Mentor and later created their own company. One thing that is certain is that France is becoming a center of excellence for embedded FPGA technology, and would seem to be an increasingly interesting technology for companies trying to pack more flexibility into their SoCs.