What needs to be considered in power exploration in finFET-based designs.
By Abishek Ranjan, Saurabh Shrimal and Sanjiv Narayan
The adoption of finFET technology has created a tectonic shift in the chip design landscape. In addition to better performance (within the same power envelope) and higher reliability, finFETs have significantly reduced the leakage power at smaller technology nodes. At the same time, the share of dynamic power dissipation continues to rise with increasing power density as more gates being packed together at smaller geometries.
Power optimization can be done at various levels of abstraction. At the system level, the designer can modify algorithms, change the pipelining, perform tradeoffs between serial vs. parallel communication/computation or specify power domains for various portions of the design. At the microarchitecture level, one can deploy techniques such as block-level clock gating, determine the memory configuration and banking, or infer FIFO’s and other communication channels. At the RTL level, clock gating and memory gating are typically used. Finally, techniques such as clock tree design, Multi-Vdd, Mult-Vth are deployed at the physical level to reduce power.
Power reduction efforts continue to focus at later phases of the design process despite the fact that the designer’s ability to reduce power dissipation declines significantly at these lower abstraction levels. A recent blind survey of 500+ RTL designers revealed that design teams often limit themselves to fine-grained power saving techniques such as clock gating that no longer provide the sole differentiators for competing in low power market.
Power optimization exploration rarely focuses on impactful micro-architectural tradeoffs such as:
• Which memory banking or register-file configuration consumes the least power?
• Would replacing a shift register with a circular buffer save power?
• What state register encoding minimizes power consumption?
• Can power be reduced by using a different bus-encoding scheme?
• What is the impact of gating off an entire block with a given expression?
• How much power could one save if we clock the design at 200 MHz instead of 250 MHz?
Designers often hesitate to explore power saving alternatives due to the lack of knowledge about which techniques are even pertinent to their design. Even if they had specific power reduction transformations identified, they lack an automated way to evaluate the power impact of such a transformation.
It is important to appreciate the effort involved in doing power exploration at higher levels of abstraction. For example, say the designer wishes to determine whether replacing a shift register with a circular buffer will reduce power. Evaluating the power impact of such a design decision will require the designer to:
1. Modify the RTL to replace the shift-register with a circular buffer;
2. Re-simulate the modified RTL to verify that design functionality has not changed;
3. Synthesize the modified RTL to generate a gate level netlist;
4. Re-simulate the generated gate-level netlist to generate gate-level switching activity, and
5. Estimate power of the gate netlist using the switching activity generated in Step 4.
The sequence of steps outlined above will require:
• multiple tools (simulation, synthesis, and power estimation);
• multiple data exchanges between tools, and
• multiple teams to get involved (verification, synthesis, and power estimation).
The turnaround time to evaluate the power impact of single tradeoff would be at least several days to weeks. Given that there is rarely be enough time in the design schedule to allow a designer to evaluate even one such power reducing transformation, evaluating multiple tradeoffs would be next to impossible.
Clearly there is a pressing need for RTL designers to be able to automatically identify power saving micro-architectural transformations, be able to rapidly explore all possible micro-architectural implementations for the design, determine the area, timing and power impact of each implementation, and then select the option that best suits their design goals.
In the second part of this series, we will introduce some of the key micro-architectural transformations that can have a significant impact on a design’s power dissipation, and present a methodology to complete this design exploration earlier in the design process.
About the Authors: Abhishek Ranjan is director of engineering at Mentor Graphics, and is based in Noida, India. Saurabh Shrimal is an application engineer at Mentor Graphics, and is based in Noida, India.