Are they all the same for established planar, FD-SOI and finFET transistors?
As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against its planar cousin.
But are various power optimization techniques for the established process nodes (e.g. 28nm and above) also applicable to the smaller non-planar geometries, or will newer methods need to be deployed? Even with moving from larger to smaller process nodes, such as 90nm to 28nm, power savings that can be achieved vary greatly.
A quick overview of techniques broken down into leakage, dynamic and multi-voltage (MV) can be viewed in Figure 1 below. Note that even though the MV techniques do help with dynamic power (e.g. low VDD operation) and leakage (e.g. shutdown), we tend to categorize them on their own since these are more advanced techniques that are controlled by power intent such as UPF.
In general, most of the techniques that are used for established planar process nodes today also apply to the smaller process geometries (e.g. FinFET and FD-SOI). For example, clock gating and clock tree synthesis do provide dynamic power savings across all process nodes. However, a technique such as lower VDD operation is much more effective for the FinFET and FD-SOI processes because they have much lower voltage thresholds where transistors can operate all the way down to 0.5V (and lower), providing significant dynamic power savings (at the expense of performance). Operation at lower voltages also makes DVFS and AVS deployment much more practical.
Reverse biasing generally is used for putting designs into standby mode, resulting in leakage savings. It was particularly effective for the larger established process nodes, providing savings of about 2X for 65nm (and greater than that for even larger processes). But it wasn’t scalable to smaller planar technologies where leakage savings reduced to only 5%-10% at 40nm, and less than 5% at 28nm. With extra routing resources required for tapping the wells, a less than 5% savings was generally not worth the tradeoff. Biasing is not an option for the 16/14nm and below FinFET process. However, biasing became viable again for the FD-SOI process where the insulator creates a buried gate below the channel, effectively providing a “vertical double gate,” providing the ability to trade off faster transistor performance (active body biasing) with reportedly up to 10X lower leakage (reverse biasing) at 28nm.
Another difference to note is that although multi-Vt (e.g. high-Vt, low-Vt) options are generally available for almost all process nodes, the number of Vt options do vary by the node. Theoretically, FinFET shouldn’t require Vt options, but there are a couple of foundries that plan to offer them, although they are going back to supply just three or four Vt options as opposed to the five or six available for the more established process nodes.
Lastly, channel-length variants, which became a standard offering at the 40nm planar nodes, are also offered for FD-SOI and FinFET processes. These are particularly effective for performing leakage recovery, or even reducing the number of Vt options used based on the target performance and power targets. The techniques and their applicability to the process nodes are summarized in Figure 2.
How applicable are all of these techniques for specific applications? Figure 3 shows the data collected from the annual Synopsys’ Global User Survey (GUS) indicating deployment of a technique across low power applications.
So when is it time move to smaller process geometries? From Synopsys’ GUS data collected from designers that made the move to FinFET, respondents indicated that their primary reason to move is for performance. But dynamic power saving and ability to operate at lower VDD were also attractive options (see Figure 4).
In summary, low power techniques are generally applicable across all process nodes, but the amount of actual savings will vary. As process geometries get smaller, some techniques are no longer applicable (e.g. biasing for 28nm) while newer techniques become more practical (e.g. low VDD and DVFS).