ReRAM Gains Even More Steam

Latest manufacturing techniques are being explored as commercial products begin rolling out.


The prospect of using the latest in finFET processing to enable embedded non-volatile memory (NWM) will be described by a team from TSMC and Tsing Hua University in Taiwan at the IEDM meeting on Dec. 8 in Washington, D.C.

Embedded NVM has been the first commercial application of ReRam, with products from Panasonic and Terrazon. Industry leaders agree the creation of NVM as a seamless addition to a microprocessor (see “ReRam Gains Steam“) is the key to success.

The paper from the TSMC team describes “A fully CMOS process compatible finFET Dielectric RRAM (called FIND RRAM) was first proposed and demonstrated by a 1kbit RRAM macro on 16nm standard finFET CMOS logicplatform. The new 16nm low-voltage FIND RRAM consists of one finFET transistor for select gate and an HfO²-based resistive film for a storage node of the cell.”

The team demonstrated the performance of a 1k bit memory macro fabricated using the 16nm finFET process at TSMC. They used the HfO² high-k gate dielectric as a layer in the resistive memory element, “with no additional process step.” The resistive element consisted of a fin, parallel to the finFET, shown below.

Figure 1: Fin in structured memory cell, from IEDM paper abstract.

The fin consists of a multilayer sandwich of TiN/ HfO2/SiO2 with the finFET metal gate and epi SiP as the two electrodes. The authors observed that “the new (device) has a very low set voltage and reset current due to field enhancement on fin corners.”

The device is the size of a 2 transistor cell, sized at 0.076 μm².

In the paper summary published before the conference, the authors showed detailed performance data. The ReRam cell is a high-resistance component. When a voltage above the set voltage (2.3V) is applied, the resistance drops by about 10x in about 50 ns. The cell is reset in 1 ms by passing a high reset current (30 uA). The high and low resistance memory cell is read by applying 0.8V VDD.

The authors mapped the High (HRS) and Low (LRS) Resistance State for the 0.999 k bits (1 fail) that yielded, and used these values to follow the life test of the part. “In 10^5 read/write cycles, there was no detectable aging of the device.” For comparison the ITRS benchmark target is 10^9 cycles.

There was a clear 5X window between HRS and LRS. The other key properties of NVM are the ability to read the cell without affecting the state of the cell. They reported “stable LCR and HCR on continuous DC read stress for 10^4 seconds” (3 hours).

They also tested accelerated data retention and showed “superior retention results…at 150˚C for 1008 hrs” (roughly 1 month), equivalent to the ITRS target over 10 years at room temperature.

Noted the authors: “In this development, a new FIND RRAM is proposed and 1kbit FIND RRAM macro has been fabricated and characterized based on the pure 16nm finFET CMOS logic process without extra mask and process step. By the RRAM ISPP algorithm, the FIND RRAM features a low operation voltage, stable LRS/HRS window, and good reliability and scalability. The results lead the FIND RRAM technology to be a promising solution in advanced finFET nodes.”

It is clearly still a research project, but the process design allows enables adding NVM capability with no additional process steps, so the cost and defect density prospects look very attractive. The positive device performance data are promising. The project demonstrates the power of teaming university researchers with state-of-the-art fabrication capability.

The paper is to be presented on Dec. 5 at IEDM and is entitled, “1Kbit FinFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process,” by Hsin Wei Pan et al of National Tsing Hua University, and Taiwan Semiconductor Manufacturing Company.