Stepping Back From Scaling

Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

Roots Of Distrust Spread

For most of the history of semiconductors there has been a persistent fear that someone would steal intellectual property from one company and sell it to another. There have been innumerable lawsuits involving corporate secrets that cross from one company to the next, and from one country to the next. The biggest concerns always were at the leading edges of technology, where those secrets w... » read more

Tech Talk: Lower Power Embedded NVM

Jen-Tai Hsu, Kilopass' vice president of engineering, talks about lower-voltage bit cells, where they fit in IoT designs and how they affect battery life. [youtube vid=dNDkuApHumU] » read more

Analog Evolves Into Mixed Signal

Predictions about the Internet of Things suggest this may be the new “Killer App,” something the semiconductor industry has long been looking for. Reinforcing the forecasts are television commercials from companies such as Cisco and GE touting the IoT’s impact on everything from jet engines to robots, capturing everyone’s imagination. New categories of products such as smartwatches will... » read more

What’s Wrong With Power Signoff

Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

Litho Is Out Of Sync

EUV’s repeated missed deadlines, and the slow-motion response by the rest of the industry to fill the void with alternatives, is having ripple effects in every facet and corner of the semiconductor industry. It’s making design harder and more expensive, introducing potential errors into the DFM flow, and greatly increasing the amount of time it takes to process wafers. It’s also adding a ... » read more

The Week In Review: System-Level Design

Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

What Can Go Wrong?

It’s no surprise that most corporate system-on-chip (SoC) design teams are dispersed throughout the world, with different functional teams often located in different countries and continents. For example, we have many customers whose SoC architecture is defined in the United States, but subsystems such as graphics and signal processing are designed elsewhere. Companies choose this approach in... » read more

Drowning In Data

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

The Rise Of Layout-Dependent Effects

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

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