The Week in Review: IoT


Investment Microsoft this week said it will spend $5 billion over four years on Internet of Things programs in research, development, and partner enablement. The company previously spent $1.5 billion on developing IoT technology. The move could pay dividends for the Microsoft Azure cloud platform and lead to wider use of Azure Stack, which pairs Microsoft software with hardware from approved p... » read more

Why All Nodes Won’t Work


A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

What’s Missing In Packaging


The growth of advanced packaging on the leading edge of design is inching backwards into older nodes. With most technology—tools, methodologies, materials and processes—this is business as usual. But in packaging, it's both counterintuitive and potentially problematic. The main reason that companies began investing in advanced packaging—OSATs, foundries, chipmakers such as Intel and Qu... » read more

Tech Talk: Smart Manufacturing


Tom Salmon, vice president of collaborative technology platforms at SEMI, examines the electronics supply chain and what the industry organization is doing to pull all of the pieces together. https://youtu.be/jWX9mayMaZo Related Stories Smart Manufacturing Gains Momentum Problems remain for legacy infrastructure, but adoption will continue to grow as gaps are identified and plugged. ... » read more

Dealing With System-Level Power


Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

Implementing High-Density-Advanced Packaging for OSATs And Foundries


HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Implementing High-Density-Advanced Packaging For OSATs And Foundries


HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Foundry Wars, Take Two


Samsung, GlobalFoundries, TSMC and Intel all have declared their intention to fill in nearly every node possible with multiple processes, different packaging options, and new materials. In fact, the only number that hasn't been taken so far is 9nm. It's not that one foundry's 10nm is the same as another's. Each company defines its nodes differently, and these days comparing nodes is almost m... » read more

Samsung Unveils Scaling, Packaging Roadmaps


Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

2.5D Adds Test Challenges


OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

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