Criticality of Wafer Edge Inspection and Metrology Data to All-Surface Defectivity Root Cause and Yield Analysis

Abstract As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi-film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, ... » read more

Debugging Debug

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Debug: Last Bastion Of Automation

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Automating Root-Cause Analysis To Reduce Time To Find Bugs by Up To 50%

If you’re spending more than 50% of your verification effort in debug, you’re not alone. For many design, verification, and embedded software engineers as well as engineers verifying complex standard protocols, debug is the primary bottleneck in verification. Most debug today is completed using the traditional methodology of print statements paired with waveforms. Given that today’s desig... » read more

Root Cause Deconvolution

Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more