FD-SOI Vs. FinFETs


Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

FD-SOI Vs. FinFETs


Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Searching For 3D Metrology


In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

Memory Architectures Undergo Changes


By Ed Sperling Memory architectures are taking some new twists. Fueled by multi-core and multiple processors, as well as some speed bumps using existing technology, SoC makers are beginning to rethink how to architect, model and assemble memory to improve speed, lower power and reduce cost. What’s unusual about all of this is that it doesn’t rely on new technology, although there certai... » read more