Negative bias temperature instability could force chipmakers to change course on materials.
As transistors shrink, not all device parameters scale at the same rate—and therein lies a potentially huge problem.
In recent years, manufacturers have been able to reduce equivalent oxide thickness (EOT) more quickly than operating voltage. As a result, the electric field present in the channel and gate dielectric has been increasing. Moreover, EOT reduction is achieved in part by reducing the thickness of the SiO2 portion of the SiO2/high-k dielectric stack comprising the gate dielectric. With a thinner interfacial oxide, tunneling into the bulk high-k oxide increases even at constant field. Increasing power density means higher operating temperatures, too, further increasing device stress.
Time-dependent dielectric breakdown, hot carrier injection, and bias temperature instability (BTI) are all field-dependent, and so all three are becoming more worrisome. Of the three, BTI increases most sharply with electric field. BTI is a shift in threshold voltage with applied stress. When the shift exceeds some specified value, typically 30 mV, the device is considered to have failed. For pFETs, the threshold voltage corresponds to a negative gate bias, and so negative bias temperature instability (NBTI) is a more serious concern than positive BTI. (The reverse is true for nFETs.)
According to IBM’s James Stathis, in work presented at the 2014 IEEE Electron Device Meeting (IEDM), the 2013 ITRS Roadmap anticipates voltage reduction sufficient to maintain nFET scaling. The field dependence of BTI is more severe in pFETs, however. NBTI may ultimately limit scaling of silicon-based pFET devices, Stathis said, requiring the introduction of alternatives like SiGe.
What does NBTI do?
The industry has been debating the mechanisms underlying NBTI for several years, only recently reaching a consensus. Empirically, though, the results are pretty grim. As devices shrink, the distribution of voltage shifts () under stress has broadened. Large devices tend to have “average” behavior, and can be seen as identical. In smaller devices, however, the time to failure due to NBTI varies widely: some devices fail very quickly, others maintain their performance over the longest times that have been tested. Conversely, when the stress is removed, some devices recover very quickly, in fractions of a second, while others fail to recover over the longest intervals tested. While failure and recovery are both bias-dependent, the time constants of the two phenomena are not the same: some devices fail quickly and recover slowly or vice versa.
The rapid partial recovery of NBTI damage complicates both research into the phenomenon and efforts to compensate for it in circuit design. For a long time, research was hindered by the difficulty of applying stress and measuring the simultaneously. Different labs reported widely varying NBTI behavior depending on the (often unknown) time interval between stress and measurement. For designers, NBTI recovery means that reliability is a function of duty cycle as well as stress. In some tests, a shorter duty cycle — corresponding to a longer recovery interval between stresses — increases lifetime by ten or even a hundred times. This duty cycle dependence, combined with extreme variability in failure times, imposes a nearly impossible task on designers: trying to achieve reliable, consistent performance when the characteristics of individual devices vary unpredictably.
How does NBTI work?
A number of mechanisms to explain NBTI behavior have been considered and discarded. One prominent model, the reaction-diffusion theory, held that trap states at the Si/SiO2 interface were created by reactions with hydrogen, diffusing to the interface from the dielectric bulk. In this model, the differences in failure and recovery time were attributed to the diffusion time between the interface and the hydrogen source. As devices shrank, though, their behavior became increasingly inconsistent with this view. Modern dielectrics simply aren’t thick enough and don’t contain enough hydrogen to support the range of diffusion distances implied by the observed NBTI time dependence. Moreover, the differences between failure time and recovery time are not consistent with a diffusion-based failure/recovery model.
Understanding NBTI in scaled devices requires measuring device performance simultaneously with stress, monitoring failure and recovery as they occur. Researchers at Infineon used a technique called time-dependent defect spectroscopy (TDDS) to do exactly that. In TDDS, a stress pulse applied to the gate is followed by continuous measurement of threshold voltage, typically for 1,000 seconds. Stress pulses ranged from 200 ns to 100 sec, and each pulse was repeated up to 256 times to evaluate charge capture and emission statistics. Production-quality scaled devices like those used in the Infineon study typically only have about two dozen interface traps, so it is feasible to monitor charge trapping and de-trapping by individual defects.
NBTI and random telegraph noise
In unbiased devices, a phenomenon called random telegraph noise (RTN) occurs as free charges, moving through the material under the influence of thermal excitation, are randomly captured by or emitted from whatever defects exist. An applied bias adds energy to this equilibrium state, exciting carriers and shifting the Fermi level relative to the energy levels of existing defects. Increasing the electric field makes more defect sites accessible to the carriers, increasing the capture rate. Each capture event shifts Vth by an amount that depends on the defect’s place in the band gap. Once the applied stress is removed de-trapping becomes more energetically favorable. The lower the electric field, the higher the carrier emission rate. Each emission event recovers a portion of the nominal Vth, again depending on the location of the defect in the band gap.
Based on their results, the Infineon group described RTN and NBTI as two aspects of the same physical mechanism. RTN represents charge trapping and de-trapping in equilibrium, while NBTI represents the same defects under stress, trying to establish a new equilibrium. Achieving equilibrium requires finite time, reflected in the varying failure and recovery times associated with NBTI stress. Later work by the same group analyzed the defects responsible for BTI in detail, concluding that the same underlying mechanism is also responsible for PBTI in nFETs.
Because both dopants and defects are distributed randomly, the distribution of stress levels at which trapping might occur is quite broad. Kaczer and colleagues observed defects that would individually cause ΔVth in excess of 30 mV after pulses as short as a fraction of a second. The recovery distribution was similarly broad, but defect capture time and emission time were not necessarily correlated. This group proposed a percolation model to describe the distribution of shifts. A continuous percolation path forms between dopant sites at the threshold voltage, allowing current flow between the source and drain. Defects obstruct this path, effectively adding an additional resistance that the carrier must overcome.
Modeling the NBTI curve
The NBTI curve for the device as a whole is defined by three types of defects: those with emission time much greater than capture time ( >> ), those with >> , and those where the two time constants are similar. If a single defect can be treated as a resistor with R = / then the behavior of a transistor depends on the sum of all defect-resistors within it. Thus, the behavior at the extremes — much larger or much smaller than — defines the shape of the NBTI curve. Measurements of the mean and the variance of the distribution can be used to extract the mean number of defects and the mean attributable to a single trapping event for a given process technology.
While detailed failure statistics will certainly help designers, the breadth of the ΔVth distribution still means that some devices will fail after relatively short times and low cumulative stresses. Worse, simply reducing the number of defects does not eliminate these early failures. This is not to say that defects don’t matter. John Boland, director of marketing for the Applied Materials Front End Products Group explained that in practice NBTI is very dependent on interface quality. A variety of plasma and heat treatments are used to densify the oxide and maintain tight interface control. Reducing the total number of defects increases the maximum lifetime and minimizes the mean shift. It just doesn’t remove the problem of early failures. No matter how small the number of defects, they will still be distributed according to Poisson statistics. As a result, both capture and emission behavior will behave stochastically as well.
Shocker: Advanced devices make life easier
There is some good news on the horizon, though. As noted above, the random distribution of dopants in the channel contributes to the broad ΔVth distribution. Reducing the channel doping — or eliminating it altogether, as fully depleted devices do — helps to narrow this variance. Indeed,Intel Corp. reports nearly negligible nFET BTI in its 22nm tri-gate devices. BTI for pFETs showed a fin orientation dependence, as expected, but was not affected by the device’s body bias.
Additional good news comes from the discovery, reported by IMEC at the 2014 IEDM, that SiGe channels, already being considered because of their improved mobility, offer substantial NBTI improvement as well. More specifically, a thin silicon passivation layer on top of an SiGe channel appears to decouple the energy levels of channel holes from those of dielectric defects. Increasing the germanium fraction increases this offset.
The bad news, of course, is that there’s always something else to worry about. While the tri-gate architecture can reduce BTI, hot carrier degradation becomes more important, especially for narrow fins. Any BTI advantages that SiGe offers will likely be at least partially offset by dielectric quality issues. But NBTI is a problem now, and those other issues lie over the horizon. For now, at least, reliability constraints on scaling seem to be manageable.