Moore’s Law Tail No Longer Wagging The Dog

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to utilize those nodes? The latter part of that question is examined in a related article, “Without Moore’s Law: EDA.”

At DAC 2014, a common theme among presenters was that fewer people will be able to utilize the emerging 16/14nm nodes, indicating that a diminished pool of people will have to pay the costs. This report, and some related articles, will examine that assertion and the impacts it may have on certain part of the industry if true.

“28nm – 22nm will be the node of choice for a long time to come because the manufacturing technology that enables 20nm and below fundamentally breaks Moore’s Law,” predicts Charlie Cheng, chief executive officer of Kilopass Technology.”

There appears to be widespread consensus behind that observation. “The shift to 20nm node is definitely different from the node shifts down to 28nm,” agrees Joseph Sawicki, vice president and general manager of the Design to Silicon Division at Mentor Graphics.

Adds George Janac, chief executive officer of Chip Path Design Systems: “It seems that the 22nm technology, single patterned with its low-leakage and low operating voltage, yet high performance is a very good technology, with probably the best PPAC (Power, Performance, Area, Cost.)”

And Gene Matter, vice president for application engineering at Docea Power, said it’s a question of diminishing returns. “The days where you could do a shrink and get a 8-10% performance gain from transistor speed, reduce or hold costs down with higher density and get some power gains from voltage scaling and transistor selection are over.”

Not everyone agrees with this premise, though. “Synopsys does not agree that Moore’s law is ending,” says John Koeter, vice president of marketing within the Solutions Group of Synopsys. “In fact, it’s just the opposite.”

And some are hedging their bets. “Many customers that we talked to at DAC were designing their current designs at 28nm,” says Anand Iyer, director of product marketing for Calypto. “They also mentioned that they are planning for the lower nodes be it 20/22nm or 14/16nm.”

The foundries fit into that camp, as well. “The CapEx investment from the major foundries into deeper sub-micron geometries build a compelling counter argument that this trend is in fact not dead nor slowing down,” points out Patrick Soheili, vice president and general manager for IP Solutions and vice president for business development at eSilicon.

But before getting too carried away with the headline statements, it is worth looking at some of the reasons that either support or refute these claims. There appear to be several factors that feed the claim indicating higher costs. The first is related to transistor costs, a second brought about by increased EDA costs and finally the increased complexity and costs associated with building chips that can make use of the new nodes.

Let’s examine the major arguments for and against.

Transistor Costs
“16nm/14nm is essentially a 20nm metal stack with a better, but more costly transistor,” says Mentor’s Sawicki. This is backed up by a forecast from the Linley Group, which shows the number of transistors that can be bought per dollar at each node likely has peaked.

Transistors that can be bought per dollar at each node.

“The 20nm node does represent a 2x scaling versus 28nm,” explains Chip Path’s Janac, “with better metal pitch. But because of double patterning, the area savings are almost all outweighed by added processing cost and complexity. The market will dictate that 20nm be at least 15% cheaper than 28nm, otherwise, the node will never see high volume.”

The 16/14nm node introduces the FinFET, but there is no shrinkage of metal pitches. So if the area is the same, the cost to process a wafer is higher. Furthermore, FinFET processing will add cost, so it is expected that this will be a more expensive process than 20nm. “16nm has a better PP, same A, but worse C, so it is likely to be used in selected markets only,” says Janac. “Information provided by Intel indicates that for 14nm, a constant area reduction of almost 2x versus 22nm is due to smaller metal pitches, with only a modest increase in processing costs.”

Which is why companies that are pushing to finFETs expect to keep plowing forward. “The FinFET enables several generations of scaling with significant power, density, and performance benefits,” says Koeter. “The cost of designing and manufacturing FinFET versus a planar bulk CMOS process is higher in absolute terms because of restrictive design rules (RDRs), double (and even triple) patterning, along with the increased gates/functions that you can put on a chip at these advanced nodes.”

So while everyone appears to agree that transistors may cost more for a while, this is not the only reason to migrate to the newer nodes. It also seems as if the 28nm to 20nm may be a one-time leveling of some of the attributes, and that they will again rise in the future.

“Even if the manufacturing costs do go up,” points out Mary Ann White, product marketing director, for Galaxy Implementation Platform at Synopsys, “there is better density (30-50%) that can make up for some of the extra costs associated with the advanced nodes, assuming that functionality on the device doesn’t change too much.”

EDA costs
On another front there is no disagreement. “Design and tooling for these advanced nodes will be much more expensive,” says Bob Smith, senior vice president of marketing and business development for Uniquify. “This is because double patterning is required, and that requires further verification.”

And beyond 14nm, multipatterning will be required because extreme ultraviolet lithography never became available, as expected.

“What we are seeing in subsequent generations is that multiple innovations are needed to get past the hurdles,” says Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy. “As we close on the major elements of 10nm and have begun on 7nm, we see this trend continue.”

Costs associated with recent process nodes

“For 10nm and smaller geometries the scaling requires more engineering effort and innovation and consequently more cost,” says Ron Moore, vice president of marketing for the Physical Design Group at ARM. “The economics of these nodes may change the pace of adoption and the first products on the node.”

There are hidden costs as well. “The flows are much more complex and layout has many more rules that need to be checked,” explains Marco Brambilla, director of engineering at Synapse Design. “Anyone can tapeout a 65nm chip, but very few teams can do the same at 14.”

Design and Complexity Considerations
Given that costs will be higher, at least in the short term, migration to new nodes must be driven by new demands and not cost reduction, which has been the major driver in the past. There is little surprise about who the early adopters of these new nodes will be.

“High-end mobile and desktop processors will always go for the latest process nodes because at that level, achieving ultimate performance efficiency is vital,” says Alexandru Voica, technology PR specialist at Imagination Technologies. “These processors end up in devices which need to top benchmarks and are driven by a high-end feature set, therefore performance and power are critical factors which model design methodologies.”

In those applications, the benefits of smaller size and lower power are critical.

“Users still want lighter weight, longer battery life and higher performance from their mobile devices, and that means more integration at newer nodes” says Carlson.”

Adds Drew Wingard CTO of Sonics: “Once the bleeding edge applications have helped the processes mature, the cost per wafer and yield rates will naturally improve and the other designs will move. The timing, however, for this move will be later and less predictable than in the past.”

Sawicki reminds us that the list of early adopters is the same as for previous nodes but asks the question, “Will the wafer start tail drop off faster as the advanced folks move to 10nm and the later adopters stay at 28nm? Our bet would be that these nodes become less costly than 28nm on a per-transistor basis in the long term, but design complexity may leave some behind on 28nm even with a modest cost advantage.”

But the improvement isn’t so easy to quantify, because there will be changes at older nodes, as well. “Many companies will stay at 28nm or older nodes, so they need to squeeze more out of their designs to reduce margins and improve their competitive edge,” claims Bruce McGaughy, chief technology officer and senior vice president of engineering of ProPlus Design Solutions. “This requires foundries to provide complete statistical models so that designers can run variation analysis to analyze the impact of process variations to their designs.”

It would seem logical that the number of companies producing designs in these new geometries will continue to decrease. “No VC wants to risk funding a company that requires at least $30 million to $40 million to get a chip designed and built,” says Charlie Kahle, chief technical officer at Synapse Design. “Only the big companies like Qualcomm, Intel, etc., will be interested in 14nm, and they will either own fabs as Intel does, or work closely with the foundries as Qualcomm already does.”

New Markets Cloud the Issue
At the same time that these issues are influencing the existing product markets, new markets are emerging that will provide a different set of drivers.

“A lot of microcontrollers today are still manufactured at 90nm or 45nm,” notes Alexandru Voica. “When targeting mass volume markets, designing low-cost processors becomes extremely important. Therefore, moving to the latest tool-chain might not always make sense from a business perspective.”

Bernard Murphy, chief technology officer for Atrenta adds that “28nm is still pretty expensive—it’s just relatively less expensive than 14nm FinFET.”

And therein lies the key for many companies. “For most applications including automotive, set-top, consumer electronics, 28nm will continue to be the process technology of choice given its relative maturity and price point,” says Aveek Sarkar, vice president of product engineering and support at Ansys-Apache.

There are other twists in this, as well. “Costs for many applications have gotten so large — and end market requirements in places like IoT are so unclear — that system companies are being increasingly forced to go back to ASICs,” says Wingard. “They will insist upon higher designer productivity to enable smaller teams to create designs more rapidly. While these designs will inherently be less optimized at the physical level, they will be more optimized at the integration level.”

And second, there is far more momentum behind stacked die than in the past because it allows a mix of all of these technologies.

“The focus will be on system integration using 2D and 3D technologies instead of just scaling transistors,” says Hem Hingarh, vice president of engineering for Synapse Design. “Most of the new products to support IoT or IoE need sensors, mixed signal chips, low-power computing engines, and application-specific embedded software. These applications do not need next-generation transistors.”