The Week In Review: Design

Mentor buys test data analysis firm; Galaxy; memory shift; heterogeneous MIPS; embedded FPGA; 10 VIPs.



Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed.


Imagination rolled out a new heterogeneous MIPS CPU with many core/multi-cluster scalable processing and real-time deterministic execution. A single multi-core cluster can utilize up to six individually configured cores. The primary system interface is ACE compatible and can be used in “many core” implementations of up to 64 clusters. The CPU is targeted at automotive, industrial automation, security, and machine learning. Mobileye will use the core in its next-gen EyeQ5 sensor fusion SoC for autonomous cars.

Achronix launched embedded FPGA (eFPGA) IP designed for compute and network acceleration applications.  Based on Achronix’s Speedster22i FPGA architecture, the IP allows customers specify the optimal die size, power consumption, and resource configuration required for their end application. It is available on TSMC 16FF+ and in development on TSMC 7nm.

Cortus released new 32-bit processor IP. Based on the Cortus v2 instruction set, the core is aimed at embedded systems requiring good computational performance while also delivering efficient silicon area and modest power dissipation. It has a Harvard architecture, sixteen 32-bit registers, a 64-bit accumulator and a 5-7 stage pipeline, as well as two execution units.

Cadence uncorked ten new VIP solutions for the latest standard protocol specifications. The full list: Ethernet 400G, Ethernet TSN, SPI NAND and Octal SPI, UFS 2.1, USB Type-C, DisplayPort (1.3, 1.4) and Embedded DisplayPort (eDP 1.4a, 1.4b), Display Stream Compression (DSC), MIPI DSI-2, and MIPI CSI-2 2.0.


Kilopass unveiled Vertical Layered Thyristor (VLT) technology for DRAM applications. According to the company, VLT eliminates the need for DRAM refresh and is compatible with existing process technologies while lowering standby power by 10X when compared to conventional DRAM at the same process node. The company plans commercialization for early 2018.


Imagination adopted Mentor Graphics’ physical RTL synthesis tool to help eliminate RTL and floor planning bottlenecks, citing significant reduction in design cycle times and number of iterations.

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