Transient power noise is one of the most limiting aspects of the chip design process with package and board inductance limiting how low the supply voltage can go.
When Intel talks, people listen. So when Intel executive VP Dadi Perlmutter said in a keynote at ISSCC in 2012 that transient power noise was one of the most limiting aspects of the chip design process—and how the package and the board inductance are limiting how low they can take the supply voltage—it showed the gravity of the challenge of effectively managing transient power. Transient power noise impacts every design today, so it is a concern on everyone’s mind.
Transient current/in-rush current really comes into play when shutdown is involved, explained Mary Ann White, director of Galaxy Implementation Platform Marketing at Synopsys. Shutdown happens with power gating (also called power switching) that acts like a switch to turn off a part of the circuit. “The in-rush current is when you turn things back on. The big concern is when you turn the power back on, there is a huge capacitive effect and everything turns on and all of a sudden you’ve got in-rush current. You want to make sure you are able to mitigate that and understand that you are not getting a huge surge on the chip.”
Aveek Sarkar, vice president of product engineering and support at Ansys Apache offered an analogy for anyone who lives in a house with old wiring: “Whenever we used to turn on too many appliances, the light used to flicker. What that essentially means is you increased the amount of load on the supply…In a chip, the analogy to flickering is that logic operations slow down from lack of instantaneous current supply to a logic state change. This is one side effect of the transient nature of a chip’s operation in which the demand current due to switching logic is changing over time. Now this current cannot be supplied instantaneously as the regular supply as the inductor throttles it down. This has to be supplied by the local capacitances that arise from intrinsic parasitic capacitances, wire coupling caps or intentional decaps. If there is insufficient amount of decap or the package inductance effect is severe, the voltage at the switching logic will be severely degraded (due to Ldi/dt effect), causing the logic to run slower or fail functionally.”
He noted that in older technology nodes there weren’t as many devices on the chip, so the current transients were not that big. Also, the decaps used to be somewhat more effective inside the chip, so even though there were transient effects such as devices turning on or off, the decaps could supply that charge or because the current did not have to come in that fast. The inductors through the package would not cause that big a drop. However, now we have chips that are operating at 2 GHz and the game has changed.
“Transient power affects the amount of noise on the chip because you have the L di/dt (inductance * delta current over delta time) that is creating a certain amount of noise,” Sarkar continued. “If inductance is very high and you’re trying to supply charge, the amount of voltage ringing that happens by the time you supply the charge makes the charge not that effective anymore. If you had a zero impedance conductance system from the battery to the chip, it gets the current in a zip and then all of a sudden the inverter can transition immediately. But that is not what is happening. The trend is that the di/dt (the transient current) is only increasing.” This is due to the fact that there are more and more devices on the chip, combined with the technology nodes pushing the I drive of these devices higher and higher.
“The impact from these transient currents is that the voltage drop noise is now higher because you have more di/dt. And because of competitive and market pressures design teams now have to reduce the cost of their package. They have to do more with less. The inductance of the package increases because if you have more things obviously you can do better, but because you have less, the inductance is higher so the L di/dt (the inductance-induced noise on the chip) is higher and the newer technology nodes have higher resistance in the vias and contacts so we typically wind up seeing more voltage drop coming from the battery to the transistors,” he explained.
All of that wouldn’t have mattered if we were still running the chip with a 2V supply, but now the supply voltage — especially for the finFET — is running at 700mV or so. 500mV of noise on a 2 V supply versus 10 mV noise on a 50 mV supply is a significant difference. “The impact is much higher. We’re not talking about slowing down a transistor anymore, we’re talking about causing a transistor to fail,” Sarkar pointed out.
Peaks and valleys
For the designers determining how to analyze and therefore make sure the design accounts for transient current peaks is a tricky feat because when the design is analyzed, explained Marko Chew, technical marketing engineer at Mentor Graphics, “it means you have to have the right scenarios since different scenarios have different switching properties. That becomes the tough part – how do you generate a realistic scenario? If you do a worst-case then everything switching is switching at the same time and that’s not going to happen so you will overdesign…The best way to do it is you run gate-level simulation, look at the output and then pick the ones that stressed the grid the worst. But most of the time when you are doing the physical design you don’t have access to that. It comes very late in the process.”
In terms of new technology to address this, Chew stressed it comes down to leveraging best practices rather than a new tool. “What you did for the last design, what is a typical flow, because most designs don’t start from scratch – they are using the previous implementation but there is some knowledge associated with that. The flip side of that is that if you are doing the same chip over and over, the same variant that might be okay. For the GPU and probably the CPU people, the next-gen is probably the same type of design. But for the SoC people where each design is basically different, then it becomes tricky.”
There are all sorts of analysis tools to be able to look at these types of things, White noted. “What happens is you have to generate what these power gate libraries will be and what their characteristics are for each of these switches so the switches will know what it would take to switch on and off. There is characterization to be able to handle that and the foundry libraries will generally provide these. You can either do these switches within a block, and that is what we call array-style switches (fine grain), or you can do it surrounding the switches in a ring style (coarse grain). You would know as it turns on and off, there is some analysis associated with that, then you can specify within a design what your IR drop maximum would be. You can either hit a target or a maximum but the foundries will tell you what their guidance is on placing the switches.” Synopsys’ technology supports both static and dynamic analysis approaches.
Apache approaches the issue by looking at statistical algorithms in order to predict the scenarios that would actually happen, working with customers to understand what could be realistic use conditions using the vectors they have to drive the simulation. Once they have the transient current in the presence of the package and the board parameters, they can determine what the voltage drop noise will be.
The impact of smaller geometries
When it comes to transient power, smaller geometries means that the interconnects used for the power grid to carry the current have less carrying capacity, so they have to be bigger to support the same amount of current, Chew noted. “Smaller geometries mean that you have to allocate more of what would have gone to routing areas to power grids. It’s going to go up to support the same gate density.”
With the addition of finFET transistors, which have higher gate capacitance, the high output drive cells have to be bigger, which means there is more current sloshing around and this means the power grid has to be larger, he said.
White noted that with smaller geometries and the use of transistors like the finFET, we will start seeing — probably due to finFET having more capacitance becasue capacitance does effect what happens during IR drops and in-rush currents, etc. — that the design will have to account for those extra types of capacitances. “That’s why you really need to make sure that you have very well characterized cells and methodologies for the analysis tools to be able to take them.”