Understanding SerDes Signal Integrity Challenges

Maintaining signal integrity is increasingly difficult as data rates move to 56Gbps and beyond.

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Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise.

There are multiple factors that can negatively influence signal integrity, thereby causing errors and system failure. These include higher bit rates, extended distances and various materials. If not properly addressed during the design stage, signal integrity issues will likely cause products to become unreliable and malfunction in the field.

As such, signal integrity has become a critical aspect of the design process. No longer limited to passive interconnect modeling, SI models the entire link, including the transmitter, receiver, clock and channel. In turn, comprehensive link analysis influences a range of design architecture, including equalization, clock, timing calibration, as well as coding and/or error correction.

Perhaps not surprisingly, maintaining SerDes signal integrity has become increasingly difficult as data rates move past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol.

After nearly fifty years, NRZ technology continues to pose significant challenges for SerDes designers. As semiconductor process nodes shrink from 28nm to deep sub-micron nodes such as 16/14nm and 10/7nm, the transistor threshold voltage (VT) is also scaling downwards. This combination of higher data rates and shrinking process nodes leaves very little margin for error. In addition, the design of circuits such as capture latches, analog-to-digital converters (ADC) and transmit drivers are particularly challenging to implement at high data rates.

With serial data rates hitting 56Gbps per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate.

Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth. More specifically, with PAM4 signaling, a 56 Gbps bit rate is transmitted at 28 GBauds and has a Nyquist frequency of 14 GHz; with NRZ signaling, the 56 Gbps bit rate is transmitted at 56 GBauds and has a Nyquist frequency of 28 GHz.

As with NRZ, PAM4 signals are also affected by jitter, channel loss and inter-symbol interference. In addition, measurements for the three eyes are further complicated by new receiver behavior, such as three slicer thresholds, individual slicer timing skew, equalization and clock and data recovery. Moreover, moving to 56G PAM4 immediately causes a loss of 9.6 dB, although there is still a demand for 30 dB+ reach for these systems.

Engineers have adapted to the various challenges of designing high-speed SerDes by upgrading the package design, thereby addressing high frequencies and tight electrical performance requirements. In addition, design teams have placed an emphasis on detailed IBIS AMI models which enable rapid, accurate and statistically significant simulation of multi-gigabit serial links.

Beyond simulations, it is important for SerDes engineers to design highly-programmable circuits, debug interfaces and utilities that enable customers to easily collate important analog and digital information. Put simply, advanced programmability and debug capabilities allow SerDes IP to be debugged during bring up, as well as adjust the performance itself if necessary.

Last but certainly not least, design experience and the ability to execute in a timely manner are essential. It is therefore critical for SerDes vendors to include a range of experts at various stages of the design, such as package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists.